diff mbox series

[PULL,06/47] target/riscv: fix za64rs enabling

Message ID	20240912052953.2552501-7-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Vladimir Isaev <vladimir.isaev@syntacore.com>, Alistair Francis <alistair.francis@wdc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 06/47] target/riscv: fix za64rs enabling Date: Thu, 12 Sep 2024 15:29:11 +1000 Message-ID: <20240912052953.2552501-7-alistair.francis@wdc.com> In-Reply-To: <20240912052953.2552501-1-alistair.francis@wdc.com> References: <20240912052953.2552501-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) \| expand [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) [PULL,02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V [PULL,03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V [PULL,04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V [PULL,05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule [PULL,06/47] target/riscv: fix za64rs enabling [PULL,07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU [PULL,08/47] target/riscv/kvm: Fix the group bit setting of AIA [PULL,09/47] target/riscv: Stop timer with infinite timecmp [PULL,10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension [PULL,11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc [PULL,12/47] target/riscv: Preliminary textra trigger CSR writting support [PULL,13/47] target/riscv: Add textra matching condition for the triggers [PULL,14/47] exec/memtxattr: add process identifier to the transaction attributes [PULL,15/47] hw/riscv: add riscv-iommu-bits.h [PULL,16/47] hw/riscv: add RISC-V IOMMU base emulation [PULL,17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device [PULL,18/47] hw/riscv: add riscv-iommu-pci reference device [PULL,19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug [PULL,20/47] test/qtest: add riscv-iommu-pci tests [PULL,21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) [PULL,22/47] hw/riscv/riscv-iommu: add ATS support [PULL,23/47] hw/riscv/riscv-iommu: add DBG support [PULL,24/47] qtest/riscv-iommu-test: add init queues test [PULL,25/47] docs/specs: add riscv-iommu [PULL,26/47] bsd-user: Implement RISC-V CPU initialization and main loop [PULL,27/47] bsd-user: Add RISC-V CPU execution loop and syscall handling [PULL,28/47] bsd-user: Implement RISC-V CPU register cloning and reset functions [PULL,29/47] bsd-user: Implement RISC-V TLS register setup [PULL,30/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection [PULL,31/47] bsd-user: Define RISC-V register structures and register copying [PULL,32/47] bsd-user: Add RISC-V signal trampoline setup function [PULL,33/47] bsd-user: Implement RISC-V sysarch system call emulation [PULL,34/47] bsd-user: Add RISC-V thread setup and initialization support [PULL,35/47] bsd-user: Define RISC-V VM parameters and helper functions [PULL,36/47] bsd-user: Define RISC-V system call structures and constants [PULL,37/47] bsd-user: Add generic RISC-V64 target definitions [PULL,38/47] bsd-user: Define RISC-V signal handling structures and constants [PULL,39/47] bsd-user: Implement RISC-V signal trampoline setup functions [PULL,40/47] bsd-user: Implement 'get_mcontext' for RISC-V [PULL,41/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV [PULL,42/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files [PULL,43/47] hw/riscv: Respect firmware ELF entry point [PULL,44/47] target: riscv: Add Svvptc extension support [PULL,45/47] target/riscv32: Fix masking of physical address [PULL,46/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled [PULL,47/47] hw/intc: riscv-imsic: Fix interrupt state updates.

Commit Message

Alistair Francis Sept. 12, 2024, 5:29 a.m. UTC

From: Vladimir Isaev <vladimir.isaev@syntacore.com>

za64rs requires priv 1.12 when enabled by priv 1.11.

This fixes annoying warning:
warning: disabling za64rs extension for hart 0x00000000 because privilege spec version does not match

on priv 1.11 CPUs.

Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features by default")
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823063431.17474-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8f21171ffa..f93bf9c221 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -115,7 +115,7 @@  const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
     ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop),
     ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
-    ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
+    ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
     ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
     ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),