[PULL,02/65] target/riscv: The whole vector register move instructions depend on vsew

From: Max Chou <max.chou@sifive.com>

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Max Chou <max.chou@sifive.com>,
 Richard Henderson <richard.henderson@linaro.org>,
 Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 02/65] target/riscv: The whole vector register move
 instructions depend on vsew
Date: Wed, 10 Jan 2024 18:56:30 +1000
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Message ID	20240110085733.1607526-3-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou <max.chou@sifive.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew Date: Wed, 10 Jan 2024 18:56:30 +1000 Message-ID: <20240110085733.1607526-3-alistair.francis@wdc.com> In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c32; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc32.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions \| expand [PULL,01/65] target/riscv: Add vill check for whole vector register move instructions [PULL,02/65] target/riscv: The whole vector register move instructions depend on vsew [PULL,03/65] target/riscv: Fix th.dcache.cval1 priviledge check [PULL,04/65] target/riscv: Not allow write mstatus_vs without RVV [PULL,05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 [PULL,06/65] target/riscv/cpu.c: fix machine IDs getters [PULL,07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 [PULL,08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 [PULL,09/65] target/riscv/kvm: change timer regs size to u64 [PULL,10/65] target/riscv/kvm: add RISCV_CONFIG_REG() [PULL,11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() [PULL,12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location [PULL,13/65] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location [PULL,14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT [PULL,15/65] hw/riscv: virt: Make few IMSIC macros and functions public [PULL,16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC [PULL,17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT [PULL,18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT [PULL,19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT [PULL,20/65] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT [PULL,21/65] hw/pci-host/gpex: Define properties for MMIO ranges [PULL,22/65] hw/riscv/virt: Update GPEX MMIO related properties [PULL,23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices [PULL,24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT [PULL,25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC [PULL,26/65] target/riscv: Add support for Zacas extension [PULL,27/65] disas/riscv: Add amocas.[w,d,q] instructions [PULL,28/65] docs/system/riscv: document acpi parameter of virt machine [PULL,29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU [PULL,30/65] target/riscv/tcg: do not use "!generic" CPU checks [PULL,31/65] target/riscv/tcg: update priv_ver on user_set extensions [PULL,32/65] target/riscv: add rv64i CPU [PULL,33/65] target/riscv: add zicbop extension flag [PULL,34/65] target/riscv/tcg: add 'zic64b' support [PULL,35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion [PULL,36/65] target/riscv: add rva22u64 profile definition [PULL,37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable [PULL,38/65] target/riscv/tcg: add user flag for profile support [PULL,39/65] target/riscv/tcg: add MISA user options hash [PULL,40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit() [PULL,41/65] target/riscv/tcg: handle profile MISA bits [PULL,42/65] target/riscv/tcg: add hash table insert helpers [PULL,43/65] target/riscv/tcg: honor user choice for G MISA bits [PULL,44/65] target/riscv/tcg: validate profiles during finalize [PULL,45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion [PULL,46/65] target/riscv: add 'rva22u64' CPU [PULL,47/65] target/riscv: implement svade [PULL,48/65] target/riscv: add priv ver restriction to profiles [PULL,49/65] target/riscv/cpu.c: finalize satp_mode earlier [PULL,50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit() [PULL,51/65] target/riscv: add satp_mode profile support [PULL,52/65] target/riscv: add 'parent' in profile description [PULL,53/65] target/riscv: add RVA22S64 profile [PULL,54/65] target/riscv: add rva22s64 cpu [PULL,55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket [PULL,56/65] linux-headers: Update to Linux v6.7-rc5 [PULL,57/65] linux-headers: riscv: add ptrace.h [PULL,58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() [PULL,59/65] target/riscv/kvm: add RVV and Vector CSR regs [PULL,60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions [PULL,61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4 [PULL,62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0 [PULL,63/65] target/riscv: Assert that the CSR numbers will be correct [PULL,64/65] target/riscv: Don't adjust vscause for exceptions [PULL,65/65] target/riscv: Ensure mideleg is set correctly on reset

[PULL,02/65] target/riscv: The whole vector register move instructions depend on vsew

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