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[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
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| 65 patches
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[PULL,65/65] target/riscv: Ensure mideleg is set correctly on reset
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,64/65] target/riscv: Don't adjust vscause for exceptions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,63/65] target/riscv: Assert that the CSR numbers will be correct
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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2024-01-10
Alistair Francis
New
[PULL,59/65] target/riscv/kvm: add RVV and Vector CSR regs
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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2024-01-10
Alistair Francis
New
[PULL,58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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-
-
2024-01-10
Alistair Francis
New
[PULL,57/65] linux-headers: riscv: add ptrace.h
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - - -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,56/65] linux-headers: Update to Linux v6.7-rc5
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - - -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,54/65] target/riscv: add rva22s64 cpu
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,53/65] target/riscv: add RVA22S64 profile
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
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2024-01-10
Alistair Francis
New
[PULL,52/65] target/riscv: add 'parent' in profile description
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,51/65] target/riscv: add satp_mode profile support
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 3 -
-
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-
2024-01-10
Alistair Francis
New
[PULL,49/65] target/riscv/cpu.c: finalize satp_mode earlier
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
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-
2024-01-10
Alistair Francis
New
[PULL,48/65] target/riscv: add priv ver restriction to profiles
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,47/65] target/riscv: implement svade
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,46/65] target/riscv: add 'rva22u64' CPU
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
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2024-01-10
Alistair Francis
New
[PULL,45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,44/65] target/riscv/tcg: validate profiles during finalize
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
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-
2024-01-10
Alistair Francis
New
[PULL,43/65] target/riscv/tcg: honor user choice for G MISA bits
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
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2024-01-10
Alistair Francis
New
[PULL,42/65] target/riscv/tcg: add hash table insert helpers
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,41/65] target/riscv/tcg: handle profile MISA bits
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 3 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 3 -
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2024-01-10
Alistair Francis
New
[PULL,39/65] target/riscv/tcg: add MISA user options hash
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 3 -
-
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2024-01-10
Alistair Francis
New
[PULL,38/65] target/riscv/tcg: add user flag for profile support
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
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-
2024-01-10
Alistair Francis
New
[PULL,37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 3 -
-
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2024-01-10
Alistair Francis
New
[PULL,36/65] target/riscv: add rva22u64 profile definition
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,34/65] target/riscv/tcg: add 'zic64b' support
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
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2024-01-10
Alistair Francis
New
[PULL,33/65] target/riscv: add zicbop extension flag
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,32/65] target/riscv: add rv64i CPU
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,31/65] target/riscv/tcg: update priv_ver on user_set extensions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
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2024-01-10
Alistair Francis
New
[PULL,30/65] target/riscv/tcg: do not use "!generic" CPU checks
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,28/65] docs/system/riscv: document acpi parameter of virt machine
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 1 3 -
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-
-
2024-01-10
Alistair Francis
New
[PULL,27/65] disas/riscv: Add amocas.[w,d,q] instructions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,26/65] target/riscv: Add support for Zacas extension
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New
[PULL,25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
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2024-01-10
Alistair Francis
New
[PULL,24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 2 -
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2024-01-10
Alistair Francis
New
[PULL,23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 1 -
-
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-
2024-01-10
Alistair Francis
New
[PULL,22/65] hw/riscv/virt: Update GPEX MMIO related properties
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - 1 -
-
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2024-01-10
Alistair Francis
New
[PULL,21/65] hw/pci-host/gpex: Define properties for MMIO ranges
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 1 -
-
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2024-01-10
Alistair Francis
New
[PULL,20/65] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 2 -
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2024-01-10
Alistair Francis
New
[PULL,19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 2 -
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2024-01-10
Alistair Francis
New
[PULL,18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 2 -
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2024-01-10
Alistair Francis
New
[PULL,17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 2 -
-
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-
2024-01-10
Alistair Francis
New
[PULL,16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - 2 -
-
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2024-01-10
Alistair Francis
New
[PULL,15/65] hw/riscv: virt: Make few IMSIC macros and functions public
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - 3 -
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2024-01-10
Alistair Francis
New
[PULL,14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
2 - - -
-
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2024-01-10
Alistair Francis
New
[PULL,13/65] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - 2 -
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2024-01-10
Alistair Francis
New
[PULL,12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - 3 -
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2024-01-10
Alistair Francis
New
[PULL,11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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2024-01-10
Alistair Francis
New
[PULL,10/65] target/riscv/kvm: add RISCV_CONFIG_REG()
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
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2024-01-10
Alistair Francis
New
[PULL,09/65] target/riscv/kvm: change timer regs size to u64
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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2024-01-10
Alistair Francis
New
[PULL,08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
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2024-01-10
Alistair Francis
New
[PULL,07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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2024-01-10
Alistair Francis
New
[PULL,06/65] target/riscv/cpu.c: fix machine IDs getters
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- 3 2 -
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2024-01-10
Alistair Francis
New
[PULL,05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
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2024-01-10
Alistair Francis
New
[PULL,04/65] target/riscv: Not allow write mstatus_vs without RVV
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
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2024-01-10
Alistair Francis
New
[PULL,03/65] target/riscv: Fix th.dcache.cval1 priviledge check
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 2 -
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2024-01-10
Alistair Francis
New
[PULL,02/65] target/riscv: The whole vector register move instructions depend on vsew
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
1 - - -
-
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2024-01-10
Alistair Francis
New
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
[PULL,01/65] target/riscv: Add vill check for whole vector register move instructions
- - 1 -
-
-
-
2024-01-10
Alistair Francis
New