Show patches with: Submitter = Alistair Francis       |    State = Action Required       |    Archived = No       |   1126 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,v2,34/47] bsd-user: Implement RISC-V TLS register setup [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,33/47] bsd-user: Implement RISC-V CPU register cloning and reset functions [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,32/47] bsd-user: Add RISC-V CPU execution loop and syscall handling [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,31/47] bsd-user: Implement RISC-V CPU initialization and main loop [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,30/47] hw/intc: riscv-imsic: Fix interrupt state updates. [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,29/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,28/47] target/riscv32: Fix masking of physical address [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,27/47] target: riscv: Add Svvptc extension support [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,26/47] hw/riscv: Respect firmware ELF entry point [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,25/47] docs/specs: add riscv-iommu [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,24/47] qtest/riscv-iommu-test: add init queues test [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,23/47] hw/riscv/riscv-iommu: add DBG support [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,22/47] hw/riscv/riscv-iommu: add ATS support [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,20/47] test/qtest: add riscv-iommu-pci tests [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,18/47] hw/riscv: add riscv-iommu-pci reference device [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,16/47] hw/riscv: add RISC-V IOMMU base emulation [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - - - --- 2024-09-24 Alistair Francis New
[PULL,v2,15/47] hw/riscv: add riscv-iommu-bits.h [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 3 - --- 2024-09-24 Alistair Francis New
[PULL,v2,14/47] exec/memtxattr: add process identifier to the transaction attributes [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 3 - --- 2024-09-24 Alistair Francis New
[PULL,v2,13/47] target/riscv: Add textra matching condition for the triggers [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,12/47] target/riscv: Preliminary textra trigger CSR writting support [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,09/47] target/riscv: Stop timer with infinite timecmp [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,08/47] target/riscv/kvm: Fix the group bit setting of AIA [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,06/47] target/riscv: fix za64rs enabling [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 2 - --- 2024-09-24 Alistair Francis New
[PULL,v2,05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) [PULL,v2,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-24 Alistair Francis New
[PULL,v2,00/47] riscv-to-apply queue - - - - --- 2024-09-24 Alistair Francis New
[PULL,47/47] hw/intc: riscv-imsic: Fix interrupt state updates. [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,46/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,45/47] target/riscv32: Fix masking of physical address [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 2 - --- 2024-09-12 Alistair Francis New
[PULL,44/47] target: riscv: Add Svvptc extension support [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,43/47] hw/riscv: Respect firmware ELF entry point [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,42/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,41/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,40/47] bsd-user: Implement 'get_mcontext' for RISC-V [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,39/47] bsd-user: Implement RISC-V signal trampoline setup functions [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,38/47] bsd-user: Define RISC-V signal handling structures and constants [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,37/47] bsd-user: Add generic RISC-V64 target definitions [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,36/47] bsd-user: Define RISC-V system call structures and constants [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,35/47] bsd-user: Define RISC-V VM parameters and helper functions [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,34/47] bsd-user: Add RISC-V thread setup and initialization support [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,33/47] bsd-user: Implement RISC-V sysarch system call emulation [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,32/47] bsd-user: Add RISC-V signal trampoline setup function [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,31/47] bsd-user: Define RISC-V register structures and register copying [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,30/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,29/47] bsd-user: Implement RISC-V TLS register setup [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,28/47] bsd-user: Implement RISC-V CPU register cloning and reset functions [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,27/47] bsd-user: Add RISC-V CPU execution loop and syscall handling [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,26/47] bsd-user: Implement RISC-V CPU initialization and main loop [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,25/47] docs/specs: add riscv-iommu [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,24/47] qtest/riscv-iommu-test: add init queues test [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,23/47] hw/riscv/riscv-iommu: add DBG support [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-12 Alistair Francis New
[PULL,22/47] hw/riscv/riscv-iommu: add ATS support [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,20/47] test/qtest: add riscv-iommu-pci tests [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-12 Alistair Francis New
[PULL,18/47] hw/riscv: add riscv-iommu-pci reference device [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-12 Alistair Francis New
[PULL,17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-12 Alistair Francis New
[PULL,16/47] hw/riscv: add RISC-V IOMMU base emulation [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - - - --- 2024-09-12 Alistair Francis New
[PULL,15/47] hw/riscv: add riscv-iommu-bits.h [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 3 - --- 2024-09-12 Alistair Francis New
[PULL,14/47] exec/memtxattr: add process identifier to the transaction attributes [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 3 - --- 2024-09-12 Alistair Francis New
[PULL,13/47] target/riscv: Add textra matching condition for the triggers [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,12/47] target/riscv: Preliminary textra trigger CSR writting support [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 2 - --- 2024-09-12 Alistair Francis New
[PULL,09/47] target/riscv: Stop timer with infinite timecmp [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 1 - --- 2024-09-12 Alistair Francis New
[PULL,08/47] target/riscv/kvm: Fix the group bit setting of AIA [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,06/47] target/riscv: fix za64rs enabling [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 2 - --- 2024-09-12 Alistair Francis New
[PULL,05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - 1 1 - --- 2024-09-12 Alistair Francis New
[PULL,04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) 1 - 1 - --- 2024-09-12 Alistair Francis New
[PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) [PULL,01/47] target/riscv: Add a property to set vl to ceil(AVL/2) - - 1 - --- 2024-09-12 Alistair Francis New
[PULL,00/47] riscv-to-apply queue - - - - --- 2024-09-12 Alistair Francis New
[v4,2/2] hw/char: sifive_uart: Print uart characters async riscv: char: Avoid dropped charecters - - 2 1 --- 2024-09-10 Alistair Francis New
[v4,1/2] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all riscv: char: Avoid dropped charecters - - 3 - --- 2024-09-10 Alistair Francis New
[v3,2/2] hw/char: sifive_uart: Print uart characters async riscv: char: Avoid dropped charecters - - 1 1 --- 2024-09-09 Alistair Francis New
[v3,1/2] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all riscv: char: Avoid dropped charecters - - 2 - --- 2024-09-09 Alistair Francis New
target: riscv: Enable Bit Manip for OpenTitan Ibex CPU target: riscv: Enable Bit Manip for OpenTitan Ibex CPU - - 1 - --- 2024-08-23 Alistair Francis New
[v2,2/2] hw/char: sifive_uart: Print uart charecters async riscv: char: Avoid dropped charecters - - - 1 --- 2024-08-19 Alistair Francis New
[v2,1/2] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all riscv: char: Avoid dropped charecters - - 2 - --- 2024-08-19 Alistair Francis New
[PULL,1/1] Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" [PULL,1/1] Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" - - 1 - --- 2024-08-19 Alistair Francis New
[PULL,0/1] riscv-to-apply queue - - - - --- 2024-08-19 Alistair Francis New
[2/2] hw/char: sifive_uart: Print uart charecters async riscv: char: Avoid dropped charecters - - - - --- 2024-08-15 Alistair Francis New
[1/2] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all riscv: char: Avoid dropped charecters - - 1 - --- 2024-08-15 Alistair Francis New
[PULL,5/5] roms/opensbi: Update to v1.5.1 [PULL,1/5] target/riscv: Remove redundant insn length check for zama16b - - 1 - --- 2024-08-06 Alistair Francis New
[PULL,4/5] target/riscv: Add asserts for out-of-bound access [PULL,1/5] target/riscv: Remove redundant insn length check for zama16b - 2 1 - --- 2024-08-06 Alistair Francis New
[PULL,3/5] target/riscv: Relax fld alignment requirement [PULL,1/5] target/riscv: Remove redundant insn length check for zama16b - - 2 - --- 2024-08-06 Alistair Francis New
[PULL,2/5] target/riscv: Add MXLEN check for F/D/Q applies to zama16b [PULL,1/5] target/riscv: Remove redundant insn length check for zama16b - - 2 - --- 2024-08-06 Alistair Francis New
[PULL,1/5] target/riscv: Remove redundant insn length check for zama16b [PULL,1/5] target/riscv: Remove redundant insn length check for zama16b - - 2 - --- 2024-08-06 Alistair Francis New
[PULL,0/5] riscv-to-apply queue - - - - --- 2024-08-06 Alistair Francis New
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