| Message ID | 20240606135454.119186-7-fea.wang@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Support RISC-V privilege 1.13 spec | expand |
On Thu, Jun 6, 2024 at 11:51 PM Fea.Wang <fea.wang@sifive.com> wrote: > > Add RISC-V privilege 1.13 support. > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > Signed-off-by: Fea.Wang <fea.wang@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Weiwei Li <liwei1518@gmail.com> > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 6 +++++- > target/riscv/tcg/tcg-cpu.c | 4 ++++ > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fd0f09c468..4760cb2cc1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1779,7 +1779,9 @@ static int priv_spec_from_str(const char *priv_spec_str) > { > int priv_version = -1; > > - if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { > + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) { > + priv_version = PRIV_VERSION_1_13_0; > + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { > priv_version = PRIV_VERSION_1_12_0; > } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { > priv_version = PRIV_VERSION_1_11_0; > @@ -1799,6 +1801,8 @@ const char *priv_spec_to_str(int priv_version) > return PRIV_VER_1_11_0_STR; > case PRIV_VERSION_1_12_0: > return PRIV_VER_1_12_0_STR; > + case PRIV_VERSION_1_13_0: > + return PRIV_VER_1_13_0_STR; > default: > return NULL; > } > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 4c6141f947..eb6f7b9d12 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) > cpu->cfg.has_priv_1_12 = true; > } > > + if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { > + cpu->cfg.has_priv_1_13 = true; > + } > + > /* zic64b is 1.12 or later */ > cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && > cpu->cfg.cbop_blocksize == 64 && > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd0f09c468..4760cb2cc1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1779,7 +1779,9 @@ static int priv_spec_from_str(const char *priv_spec_str) { int priv_version = -1; - if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) { + priv_version = PRIV_VERSION_1_13_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { priv_version = PRIV_VERSION_1_12_0; } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { priv_version = PRIV_VERSION_1_11_0; @@ -1799,6 +1801,8 @@ const char *priv_spec_to_str(int priv_version) return PRIV_VER_1_11_0_STR; case PRIV_VERSION_1_12_0: return PRIV_VER_1_12_0_STR; + case PRIV_VERSION_1_13_0: + return PRIV_VER_1_13_0_STR; default: return NULL; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4c6141f947..eb6f7b9d12 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) cpu->cfg.has_priv_1_12 = true; } + if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { + cpu->cfg.has_priv_1_13 = true; + } + /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && cpu->cfg.cbop_blocksize == 64 &&