Show patches with: Submitter = Fea Wang       |    State = Action Required       |    Archived = No       |   66 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v5,6/6] target/riscv: Check svukte is not enabled in RV32 Introduce svukte ISA extension - - 1 - --- 2024-12-03 Fea Wang New
[v5,5/6] target/riscv: Expose svukte ISA extension Introduce svukte ISA extension - - 3 - --- 2024-12-03 Fea Wang New
[v5,4/6] target/riscv: Check memory access to meet svukte rule Introduce svukte ISA extension - - 3 - --- 2024-12-03 Fea Wang New
[v5,3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 4 - --- 2024-12-03 Fea Wang New
[v5,2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 4 - --- 2024-12-03 Fea Wang New
[v5,1/6] target/riscv: Add svukte extension capability variable Introduce svukte ISA extension - - 4 - --- 2024-12-03 Fea Wang New
[v4,6/6] target/riscv: Check svukte is not enabled in RV32 Introduce svukte ISA extension - - - - --- 2024-11-20 Fea Wang New
[v4,5/6] target/riscv: Expose svukte ISA extension Introduce svukte ISA extension - - 3 - --- 2024-11-20 Fea Wang New
[v4,4/6] target/riscv: Check memory access to meet svukte rule Introduce svukte ISA extension - - 3 - --- 2024-11-20 Fea Wang New
[v4,3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 4 - --- 2024-11-20 Fea Wang New
[v4,2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 4 - --- 2024-11-20 Fea Wang New
[v4,1/6] target/riscv: Add svukte extension capability variable Introduce svukte ISA extension - - 4 - --- 2024-11-20 Fea Wang New
[1/1] hw/net: Support Marvell 88E1111 phy driver [1/1] hw/net: Support Marvell 88E1111 phy driver - - - - --- 2024-11-15 Fea Wang New
[v3,5/5] target/riscv: Expose svukte ISA extension Introduce svukte ISA extension - - 3 - --- 2024-11-12 Fea Wang New
[v3,4/5] target/riscv: Check memory access to meet svukte rule Introduce svukte ISA extension - - 2 - --- 2024-11-12 Fea Wang New
[v3,3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 4 - --- 2024-11-12 Fea Wang New
[v3,2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 4 - --- 2024-11-12 Fea Wang New
[v3,1/5] target/riscv: Add svukte extension capability variable Introduce svukte ISA extension - - 4 - --- 2024-11-12 Fea Wang New
[v2,5/5] target/riscv: Expose svukte ISA extension Introduce svukte ISA extension - - 2 - --- 2024-11-08 Fea Wang New
[v2,4/5] target/riscv: Check memory access to meet svuket rule Introduce svukte ISA extension - - 1 - --- 2024-11-08 Fea Wang New
[v2,3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 3 - --- 2024-11-08 Fea Wang New
[v2,2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 3 - --- 2024-11-08 Fea Wang New
[v2,1/5] target/riscv: Add svukte extension capability variable Introduce svukte ISA extension - - 3 - --- 2024-11-08 Fea Wang New
[1/1] softmmu/physmem.c: Keep transaction attribute in address_space_map() Keep transaction attribute in address_space_map() - 1 1 - --- 2024-09-12 Fea Wang New
[5/5] target/riscv: Expose svukte ISA extension Introduce svukte ISA extension - - 2 - --- 2024-09-03 Fea Wang New
[4/5] target/riscv: Check memory access to meet svuket rule Introduce svukte ISA extension - - 1 - --- 2024-09-03 Fea Wang New
[3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 2 - --- 2024-09-03 Fea Wang New
[2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Introduce svukte ISA extension - - 2 - --- 2024-09-03 Fea Wang New
[1/5] target/riscv: Add svukte extension capability variable Introduce svukte ISA extension - - 2 - --- 2024-09-03 Fea Wang New
[v3,3/3] hw/net: Fix the transmission return size hw/dma: Add error handling for loading descriptions failing - - 2 - --- 2024-06-13 Fea Wang New
[v3,2/3] hw/dma: Add a trace log for a description loading failure hw/dma: Add error handling for loading descriptions failing - - 3 - --- 2024-06-13 Fea Wang New
[v3,1/3] hw/dma: Enhance error handling in loading description hw/dma: Add error handling for loading descriptions failing - - 1 - --- 2024-06-13 Fea Wang New
[v4,6/6] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 4 - --- 2024-06-06 Fea Wang New
[v4,5/6] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-06 Fea Wang New
[v4,4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-06 Fea Wang New
[v4,3/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-06 Fea Wang New
[v4,2/6] target/riscv: Define macros and variables for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 4 - --- 2024-06-06 Fea Wang New
[v4,1/6] target/riscv: Reuse the conversion function of priv_spec target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-06 Fea Wang New
[v2,3/3] hw/net: Fix the transmission return size hw/dma: Add error handling for loading descriptions failing - - 2 - --- 2024-06-04 Fea Wang New
[v2,2/3] hw/dma: Add a trace log for a description loading failure hw/dma: Add error handling for loading descriptions failing - - 2 - --- 2024-06-04 Fea Wang New
[v2,1/3] hw/dma: Enhance error handling in loading description hw/dma: Add error handling for loading descriptions failing - - 2 - --- 2024-06-04 Fea Wang New
[v3,6/6] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-04 Fea Wang New
[v3,5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-04 Fea Wang New
[v3,4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-04 Fea Wang New
[v3,3/6] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-04 Fea Wang New
[v3,2/6] target/riscv: Define macros and variables for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 4 - --- 2024-06-04 Fea Wang New
[v3,1/6] target/riscv: Reuse the conversion function of priv_spec target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-06-04 Fea Wang New
[4/4] hw/net: Fix the transmission return size hw/dma: Add error handling for loading descriptions failing - - 2 - --- 2024-06-03 Fea Wang New
[3/4] hw/dma: Add a trace log for a description loading failure hw/dma: Add error handling for loading descriptions failing - - 2 - --- 2024-06-03 Fea Wang New
[2/4] hw/dma: Break the loop when loading descriptions fails hw/dma: Add error handling for loading descriptions failing - - 1 - --- 2024-06-03 Fea Wang New
[1/4] hw/dma: Enhance error handling in loading description hw/dma: Add error handling for loading descriptions failing - - 1 - --- 2024-06-03 Fea Wang New
[RESEND,v2,5/5] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[RESEND,v2,4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[RESEND,v2,3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[RESEND,v2,2/5] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 4 - --- 2024-05-15 Fea Wang New
[RESEND,v2,1/5] target/riscv: Reuse the conversion function of priv_spec target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[5/5] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[2/5] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-15 Fea Wang New
[1/5] target/riscv: Reuse the conversion function of priv_spec target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-15 Fea Wang New
[5/5] target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New
[4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New
[3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New
[2/5] target/riscv: Support the version for ss1p13 target/riscv: Support RISC-V privilege 1.13 spec - - 3 - --- 2024-05-10 Fea Wang New
[1/5] target/riscv: Reuse the conversion function of priv_spec and string target/riscv: Support RISC-V privilege 1.13 spec - - 2 - --- 2024-05-10 Fea Wang New