| Message ID | 20240711082912.761806-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark | expand |
LGTM juzhe.zhong@rivai.ai From: pan2.li Date: 2024-07-11 16:29 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark From: Pan Li <pan2.li@intel.com> This patch would like to add the test cases for the vector .SAT_SUB in the zip benchmark. Aka: Form in zip benchmark: #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ { \ T2 a; \ T1 *p = x; \ do { \ a = *--p; \ *p = (T1)(a >= b ? a - b : 0); \ } while (--limit); \ } DEF_VEC_SAT_U_SUB_ZIP(uint8_t, uint16_t) vec_sat_u_sub_uint16_t_uint32_t_fmt_zip: ... vsetvli a4,zero,e32,m1,ta,ma vmv.v.x v6,a1 vsetvli zero,zero,e16,mf2,ta,ma vid.v v2 li a4,-1 vnclipu.wi v6,v6,0 // .SAT_TRUNC .L3: vle16.v v3,0(a3) vrsub.vx v5,v2,a6 mv a7,a4 addw a4,a4,t3 vrgather.vv v1,v3,v5 vssubu.vv v1,v1,v6 // .SAT_SUB vrgather.vv v3,v1,v5 vse16.v v3,0(a3) sub a3,a3,t1 bgtu t4,a4,.L3 Passed the rv64gcv tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test data for .SAT_SUB in zip benchmark. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com> --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 18 +++++ .../rvv/autovec/binop/vec_sat_binary_vx.h | 22 +++++ .../riscv/rvv/autovec/binop/vec_sat_data.h | 81 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub_zip-run.c | 16 ++++ .../rvv/autovec/binop/vec_sat_u_sub_zip.c | 18 +++++ 5 files changed, 155 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 10459807b2c..416a1e49a47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -322,6 +322,19 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ +{ \ + T2 a; \ + T1 *p = x; \ + do { \ + a = *--p; \ + *p = (T1)(a >= b ? a - b : 0); \ + } while (--limit); \ +} +#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2) + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -352,6 +365,11 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ + vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) +#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \ + RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ + /******************************************************************************/ /* Saturation Sub Truncated (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h new file mode 100644 index 00000000000..d238c6392de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h @@ -0,0 +1,22 @@ +#ifndef HAVE_DEFINED_VEC_SAT_BINARY_VX_H +#define HAVE_DEFINED_VEC_SAT_BINARY_VX_H + +int +main () +{ + unsigned i, k; + T d; + + for (i = 0; i < sizeof (DATA) / sizeof (DATA[0]); i++) + { + RUN_BINARY_VX (&d.x[N], d.b, N); + + for (k = 0; k < N; k++) + if (d.x[k] != d.expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h index 0146138a3c5..1db0f173c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h @@ -253,4 +253,85 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] = }, }; +#define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data +#define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \ + TEST_BINARY_DATA_NAME(T1, T2, NAME) + +#define TEST_ZIP_STRUCT_NAME(T1, T2) test_##T1##_##T2##_zip_s +#define TEST_ZIP_STRUCT_DECL(T1, T2) struct TEST_ZIP_STRUCT_NAME(T1, T2) +#define TEST_ZIP_STRUCT(T1, T2) \ + TEST_ZIP_STRUCT_DECL(T1, T2) \ + { \ + T1 x[N]; \ + T2 b; \ + T1 expect[N]; \ + }; + +TEST_ZIP_STRUCT (uint16_t, uint32_t) + +TEST_ZIP_STRUCT_DECL(uint16_t, uint32_t) \ + TEST_BINARY_DATA_NAME(uint16_t, uint32_t, zip)[] = +{ + { + { /* x. */ + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + 1, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 1, 2, 8, + 65535, 1, 2, 8, + 65535, 1, 2, 8, + 65535, 1, 2, 8, + }, + 65536, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + }, + 65535, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + }, + 65500, /* b. */ + { /* expect. */ + 35, 0, 0, 0, + 35, 0, 0, 0, + 35, 0, 0, 0, + 35, 0, 0, 0, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c new file mode 100644 index 00000000000..456d99a8d5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 uint16_t +#define T2 uint32_t + +DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) + +#define DATA TEST_BINARY_DATA_NAME_WRAP(T1, T2, zip) +#define T TEST_ZIP_STRUCT_DECL(T1, T2) +#define RUN_BINARY_VX(x, b, N) RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) + +#include "vec_sat_binary_vx.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c new file mode 100644 index 00000000000..cd9ea0e1c76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_uint32_t_fmt_zip: +** ... +** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... +** vrgather\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, July 11, 2024 6:32 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
LGTM
Hi Pan, This patch appears to be tripping up our postcommit for building linux with vector https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1325. FAIL: gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c execution test Looking at the logs, the test fails due to the __builtin_abort call when d.x[k] != d.expect[k]. > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h > new file mode 100644 > index 00000000000..d238c6392de > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h > @@ -0,0 +1,22 @@ > +#ifndef HAVE_DEFINED_VEC_SAT_BINARY_VX_H > +#define HAVE_DEFINED_VEC_SAT_BINARY_VX_H > + > +int > +main () > +{ > + unsigned i, k; > + T d; > + > + for (i = 0; i < sizeof (DATA) / sizeof (DATA[0]); i++) > + { > + RUN_BINARY_VX (&d.x[N], d.b, N); > + > + for (k = 0; k < N; k++) > + if (d.x[k] != d.expect[k]) > + __builtin_abort (); > + } > + > + return 0; > +} > + > +#endif I think you forgot to initialize d = data[i] in the loop? Edwin
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 10459807b2c..416a1e49a47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -322,6 +322,19 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ +{ \ + T2 a; \ + T1 *p = x; \ + do { \ + a = *--p; \ + *p = (T1)(a >= b ? a - b : 0); \ + } while (--limit); \ +} +#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2) + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -352,6 +365,11 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ + vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) +#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \ + RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ + /******************************************************************************/ /* Saturation Sub Truncated (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h new file mode 100644 index 00000000000..d238c6392de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h @@ -0,0 +1,22 @@ +#ifndef HAVE_DEFINED_VEC_SAT_BINARY_VX_H +#define HAVE_DEFINED_VEC_SAT_BINARY_VX_H + +int +main () +{ + unsigned i, k; + T d; + + for (i = 0; i < sizeof (DATA) / sizeof (DATA[0]); i++) + { + RUN_BINARY_VX (&d.x[N], d.b, N); + + for (k = 0; k < N; k++) + if (d.x[k] != d.expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h index 0146138a3c5..1db0f173c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h @@ -253,4 +253,85 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] = }, }; +#define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data +#define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \ + TEST_BINARY_DATA_NAME(T1, T2, NAME) + +#define TEST_ZIP_STRUCT_NAME(T1, T2) test_##T1##_##T2##_zip_s +#define TEST_ZIP_STRUCT_DECL(T1, T2) struct TEST_ZIP_STRUCT_NAME(T1, T2) +#define TEST_ZIP_STRUCT(T1, T2) \ + TEST_ZIP_STRUCT_DECL(T1, T2) \ + { \ + T1 x[N]; \ + T2 b; \ + T1 expect[N]; \ + }; + +TEST_ZIP_STRUCT (uint16_t, uint32_t) + +TEST_ZIP_STRUCT_DECL(uint16_t, uint32_t) \ + TEST_BINARY_DATA_NAME(uint16_t, uint32_t, zip)[] = +{ + { + { /* x. */ + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + 1, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 1, 2, 8, + 65535, 1, 2, 8, + 65535, 1, 2, 8, + 65535, 1, 2, 8, + }, + 65536, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + }, + 65535, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + }, + 65500, /* b. */ + { /* expect. */ + 35, 0, 0, 0, + 35, 0, 0, 0, + 35, 0, 0, 0, + 35, 0, 0, 0, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c new file mode 100644 index 00000000000..456d99a8d5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 uint16_t +#define T2 uint32_t + +DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) + +#define DATA TEST_BINARY_DATA_NAME_WRAP(T1, T2, zip) +#define T TEST_ZIP_STRUCT_DECL(T1, T2) +#define RUN_BINARY_VX(x, b, N) RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) + +#include "vec_sat_binary_vx.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c new file mode 100644 index 00000000000..cd9ea0e1c76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_uint32_t_fmt_zip: +** ... +** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... +** vrgather\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */