Toggle navigation
Patchwork
GNU Compiler Collection
Patches
Bundles
About this project
Login
Register
Mail settings
Show patches with
: Submitter =
Li, Pan2
| State =
Action Required
| Archived =
No
| 348 patches
Series
Submitter
State
any
Action Required
New
Under Review
Accepted
Rejected
RFC
Not Applicable
Changes Requested
Awaiting Upstream
Superseded
Deferred
Needs Review / ACK
Handled Elsewhere
Search
Archived
No
Yes
Both
Delegate
------
Nobody
jgarzik
arnd
ymano
smfrench
jlayton
tseliot
ogasawara
amitk
awhitcroft
mst
dayangkun
jwboyer
jwboyer
colinking
colinking
azummo
dwmw2
rtg
sconklin
smb
aliguori
bradf
demarchi
ms
bhundven
chbs
kengyu
kadlec
pdp
regit
jabk
laforge
laforge
tonyb
alai
zecke
zecke
__damien__
luka
luka
prafulla@marvell.com
cyrus
PeterHuewe
kiho
jow
jow
ypwong
nico
dedeckeh
dedeckeh
yousong
yousong
tomcwarren
mb
mrchuck
vineetg76
computersforpeace
Noltari
Noltari
patrick_delaunay
ee07b291
ldir
ldir
stefanct
zhouhan
carldani
blp
ffainelli
ffainelli
regXboi
bbrezillon
pravin
mkp
jpettit
mkresin
mkresin
thess
thess
fbarrat
fbarrat
phil
linville
jesse
tjaalton
esben
abrodkin
abrodkin
diproiettod
tbot
stephenfin
vriera
darball1
sammj
ajd
jogo
jogo
bhelgaas
blogic
blogic
tagr
tagr
tagr
oohal
russellb
ptomsich
agraf
joestringer
mwalle
naveen
pchotard
pepe2k
pepe2k
arj
arj
davem
davem
davem
andmur01
amitay
matttbe
pabeni
istokes
tytso
aparcar
Ansuel
goliath
martineau
danielschwierzeck
mariosix
dcaratti
hs
ovsrobot
ovsrobot
tpetazzoni
XiaoYang
mkorpershoek
aserdean
marex
khem
liwang
mmichelson
danielhb
groug
robimarko
npiggin
apritzel
pareddja
atishp
netdrv
mkubecek
stintel
stintel
jkicinski
cpitchen
maximeh
dsa
jstancek
pm215
bpf
jonhunter
shettyg
lorpie01
acelan
wigyori
wigyori
apopple
dja
alexhung
lynxis
lynxis
brgl
brgl
peda
akodanev
narmstrong
0andriy
981213
monstr
snowpatch_ozlabs
snowpatch_ozlabs
snowpatch_ozlabs
aivanov
atishp04
shemminger
blocktrron
vigneshr
mraynal
chunkeey
stewart
stewart
xypron
kabel
ukleinek
ukleinek
prom
horms
rfried
sjg
ivanhu
freenix
Jaehoon
rsalvaterra
adrianschmutzler
jacmet
hegdevasant
hegdevasant
jagan
ag
metan
akumar
ehristev
bmeng
wsa
rmilecki
rmilecki
kevery
arbab
svanheule
abelloni
rw
rw
apconole
pablo
pablo
wbx
trini
legoater
legoater
legoater
chleroy
bjonglez
ynezz
pevik
sbabic
sbabic
aik
xback
xback
richiejp
dangole
dangole
forty
anuppatel
anuppatel
next_ghost
acer
echaudron
Hauke
Hauke
benh
rgrimm
segher
pratyush
passgat
jms
jms
jms
mans0n
ruscur
jk
jk
jk
jk
Andes
jmberg
numans
festevam
ymorin
ymorin
xuyang
linusw
linusw
kubu
tambarus
matthias_bgg
conchuod
strlen
strlen
imaximets
spectrum
dceara
pbrobinson
stroese
krzk
apalos
cazzacarna
neocturne
aldot
TIENFONG
mpe
sfr
galak
ktraynor
arnout
robh
anguy11
calebccff
nbd
nbd
paulus
jm
Apply
«
1
2
3
4
»
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v2,2/2] Match: Support form 3 for scalar signed integer .SAT_ADD
[v2,1/2] Genmatch: Support control flow graph case 1 for phi on condition
- - - -
-
-
-
2024-09-05
Li, Pan2
New
[v2,1/2] Genmatch: Support control flow graph case 1 for phi on condition
[v2,1/2] Genmatch: Support control flow graph case 1 for phi on condition
- - - -
-
-
-
2024-09-05
Li, Pan2
New
[v1] RISC-V: Fix SAT_* dump check failure due to middle-end change.
[v1] RISC-V: Fix SAT_* dump check failure due to middle-end change.
- - - -
-
-
-
2024-09-05
Li, Pan2
New
[v1,2/2] Match: Support form 3 for scalar signed integer .SAT_ADD
[v1,1/2] Genmatch: Support new flow for phi on condition
- - - -
-
-
-
2024-09-04
Li, Pan2
New
[v1,1/2] Genmatch: Support new flow for phi on condition
[v1,1/2] Genmatch: Support new flow for phi on condition
- - - -
-
-
-
2024-09-04
Li, Pan2
New
[v1] Match: Support form 2 for scalar signed integer .SAT_ADD
[v1] Match: Support form 2 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-09-03
Li, Pan2
New
[v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD
[v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD
- - - -
-
-
-
2024-09-02
Li, Pan2
New
[v1,2/2] Match: Add int type fits check for form 2 of .SAT_SUB imm operand
[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand
- - - -
-
-
-
2024-09-02
Li, Pan2
New
[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand
[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand
- - - -
-
-
-
2024-09-02
Li, Pan2
New
[v1] Vect: Support form 1 of vector signed integer .SAT_ADD
[v1] Vect: Support form 1 of vector signed integer .SAT_ADD
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v1] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64
[v1] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM
[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
- - - -
-
-
-
2024-08-30
Li, Pan2
New
[v2,2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3
[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-29
Li, Pan2
New
[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-29
Li, Pan2
New
[v1] RISC-V: Support form 1 of integer scalar .SAT_ADD
[v1] RISC-V: Support form 1 of integer scalar .SAT_ADD
- - - -
-
-
-
2024-08-29
Li, Pan2
New
[v3] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
[v3] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
- - - -
-
-
-
2024-08-28
Li, Pan2
New
[v4] Match: Support form 1 for scalar signed integer .SAT_ADD
[v4] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v2] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
[v2] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD
- - - -
-
-
-
2024-08-27
Li, Pan2
New
[v1] RISC-V: Support IMM for operand 1 of ussub pattern
[v1] RISC-V: Support IMM for operand 1 of ussub pattern
- - - -
-
-
-
2024-08-26
Li, Pan2
New
[v2] Match: Add int type fits check for .SAT_ADD imm operand
[v2] Match: Add int type fits check for .SAT_ADD imm operand
- - - -
-
-
-
2024-08-26
Li, Pan2
New
[v3] Match: Support form 1 for scalar signed integer .SAT_ADD
[v3] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-26
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
- - - -
-
-
-
2024-08-25
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4
- - - -
-
-
-
2024-08-25
Li, Pan2
New
[v1] Match: Add type check for .SAT_ADD imm operand
[v1] Match: Add type check for .SAT_ADD imm operand
- - - -
-
-
-
2024-08-24
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-21
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-21
Li, Pan2
New
[v1] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]
[v1] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]
- - - -
-
-
-
2024-08-20
Li, Pan2
New
[v1] Match: Support form 4 for unsigned integer .SAT_TRUNC
[v1] Match: Support form 4 for unsigned integer .SAT_TRUNC
- - - -
-
-
-
2024-08-20
Li, Pan2
New
[v3] RISC-V: Support IMM for operand 0 of ussub pattern
[v3] RISC-V: Support IMM for operand 0 of ussub pattern
- - - -
-
-
-
2024-08-19
Li, Pan2
New
[v2] Test: Move pr116278 run test to dg/torture [NFC]
[v2] Test: Move pr116278 run test to dg/torture [NFC]
- - - -
-
-
-
2024-08-19
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-19
Li, Pan2
New
[v1] Test: Move pr116278 run test to c-torture [NFC]
[v1] Test: Move pr116278 run test to c-torture [NFC]
- - - -
-
-
-
2024-08-18
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-18
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-18
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-17
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2
- - - -
-
-
-
2024-08-17
Li, Pan2
New
[v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]
[v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]
- - - -
-
-
-
2024-08-17
Li, Pan2
New
[v3] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
[v3] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
- - - -
-
-
-
2024-08-13
Li, Pan2
New
[v2] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
[v2] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
- - - -
-
-
-
2024-08-11
Li, Pan2
New
[v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect
[v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect
- - - -
-
-
-
2024-08-10
Li, Pan2
New
[v1] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
[v1] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278]
- - - -
-
-
-
2024-08-09
Li, Pan2
New
[v2] Match: Support form 1 for scalar signed integer .SAT_ADD
[v2] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-07
Li, Pan2
New
[v2] Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]
[v2] Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]
- - - -
-
-
-
2024-08-06
Li, Pan2
New
[v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change
[v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end change
- - - -
-
-
-
2024-08-05
Li, Pan2
New
[v1] Match: Support form 1 for scalar signed integer .SAT_ADD
[v1] Match: Support form 1 for scalar signed integer .SAT_ADD
- - - -
-
-
-
2024-08-05
Li, Pan2
New
[v2] RISC-V: Support IMM for operand 0 of ussub pattern
[v2] RISC-V: Support IMM for operand 0 of ussub pattern
- - - -
-
-
-
2024-08-04
Li, Pan2
New
[v1] Match: Add type_has_mode_precision_p check for SAT_TRUNC [PR116202]
[v1] Match: Add type_has_mode_precision_p check for SAT_TRUNC [PR116202]
- - - -
-
-
-
2024-08-04
Li, Pan2
New
[v1] RISC-V: Support IMM for operand 0 of ussub pattern
[v1] RISC-V: Support IMM for operand 0 of ussub pattern
- - - -
-
-
-
2024-08-03
Li, Pan2
New
[v1] RISC-V: Take Xmode instead of Pmode for ussub expanding
[v1] RISC-V: Take Xmode instead of Pmode for ussub expanding
- - - -
-
-
-
2024-07-30
Li, Pan2
New
[v2] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
[v2] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
- - - -
-
-
-
2024-07-30
Li, Pan2
New
[v1] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
[v1] Internal-fn: Handle vector bool type for type strict match mode [PR116103]
- - - -
-
-
-
2024-07-29
Li, Pan2
New
[v1] Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMM
[v1] Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMM
- - - -
-
-
-
2024-07-28
Li, Pan2
New
[v1] Match: Support .SAT_SUB with IMM op for form 1-4
[v1] Match: Support .SAT_SUB with IMM op for form 1-4
- - - -
-
-
-
2024-07-26
Li, Pan2
New
[v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar
[v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-23
Li, Pan2
New
[v1] RISC-V: Rearrange the test helper files for vector .SAT_*
[v1] RISC-V: Rearrange the test helper files for vector .SAT_*
- - - -
-
-
-
2024-07-21
Li, Pan2
New
[v2] Internal-fn: Only allow type matches mode for internal fn[PR115961]
[v2] Internal-fn: Only allow type matches mode for internal fn[PR115961]
- - - -
-
-
-
2024-07-19
Li, Pan2
New
[v1] Internal-fn: Only allow modes describe types for internal fn[PR115961]
[v1] Internal-fn: Only allow modes describe types for internal fn[PR115961]
- - - -
-
-
-
2024-07-19
Li, Pan2
New
[v1] Match: Only allow single use of MIN_EXPR for SAT_TRUNC form 2 [PR115863]
[v1] Match: Only allow single use of MIN_EXPR for SAT_TRUNC form 2 [PR115863]
- - - -
-
-
-
2024-07-18
Li, Pan2
New
[v2] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
[v2] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
- - - -
-
-
-
2024-07-18
Li, Pan2
New
[v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
[v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes
- - - -
-
-
-
2024-07-18
Li, Pan2
New
[v1] Match: Bugfix .SAT_TRUNC honor types has no mode precision [PR115961]
[v1] Match: Bugfix .SAT_TRUNC honor types has no mode precision [PR115961]
- - - -
-
-
-
2024-07-17
Li, Pan2
New
[v3] RISC-V: Implement the .SAT_TRUNC for scalar
[v3] RISC-V: Implement the .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-15
Li, Pan2
New
[v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
[v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
- - - -
-
-
-
2024-07-11
Li, Pan2
New
[v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call
[v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call
- - - -
-
-
-
2024-07-10
Li, Pan2
New
[v3] Vect: Optimize truncation for .SAT_SUB operands
[v3] Vect: Optimize truncation for .SAT_SUB operands
- - - -
-
-
-
2024-07-09
Li, Pan2
New
[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
[v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v2] RISC-V: Implement .SAT_TRUNC for vector unsigned int
[v2] RISC-V: Implement .SAT_TRUNC for vector unsigned int
- - - -
-
-
-
2024-07-08
Li, Pan2
New
[v2] Vect: Distribute truncation into .SAT_SUB operands
[v2] Vect: Distribute truncation into .SAT_SUB operands
- - - -
-
-
-
2024-07-05
Li, Pan2
New
[v1] Match: Support form 2 for the .SAT_TRUNC
[v1] Match: Support form 2 for the .SAT_TRUNC
- - - -
-
-
-
2024-07-05
Li, Pan2
New
[v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
[v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
- - - -
-
-
-
2024-07-05
Li, Pan2
New
[v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]
[v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]
- - - -
-
-
-
2024-07-03
Li, Pan2
New
[v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
[v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
- - - -
-
-
-
2024-07-03
Li, Pan2
New
[v2] RISC-V: Implement the .SAT_TRUNC for scalar
[v2] RISC-V: Implement the .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-03
Li, Pan2
New
[v2] Vect: Support IFN SAT_TRUNC for unsigned vector int
[v2] Vect: Support IFN SAT_TRUNC for unsigned vector int
- - - -
-
-
-
2024-07-03
Li, Pan2
New
[v1] Vect: Support IFN SAT_TRUNC for unsigned vector int
[v1] Vect: Support IFN SAT_TRUNC for unsigned vector int
- - - -
-
-
-
2024-07-02
Li, Pan2
New
[v2] RISC-V: Implement the .SAT_TRUNC for scalar
[v2] RISC-V: Implement the .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-02
Li, Pan2
New
[v1] Match: Allow more types truncation for .SAT_TRUNC
[v1] Match: Allow more types truncation for .SAT_TRUNC
- - - -
-
-
-
2024-07-02
Li, Pan2
New
[v1] RISC-V: Implement the .SAT_TRUNC for scalar
[v1] RISC-V: Implement the .SAT_TRUNC for scalar
- - - -
-
-
-
2024-07-01
Li, Pan2
New
[v1,4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
[v1,1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-01
Li, Pan2
New
[v1,3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3
[v1,1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-01
Li, Pan2
New
[v1,2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2
[v1,1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-01
Li, Pan2
New
[v1,1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
[v1,1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
- - - -
-
-
-
2024-07-01
Li, Pan2
New
[v1] Vect: Distribute truncation into .SAT_SUB operands
[v1] Vect: Distribute truncation into .SAT_SUB operands
- - - -
-
-
-
2024-06-30
Li, Pan2
New
[v1] Match: Support imm form for unsigned scalar .SAT_ADD
[v1] Match: Support imm form for unsigned scalar .SAT_ADD
- - - -
-
-
-
2024-06-28
Li, Pan2
New
[v2] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int
[v2] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int
- - - -
-
-
-
2024-06-27
Li, Pan2
New
[v3] Vect: Support truncate after .SAT_SUB pattern in zip
[v3] Vect: Support truncate after .SAT_SUB pattern in zip
- - - -
-
-
-
2024-06-27
Li, Pan2
New
[v1] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int
[v1] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int
- - - -
-
-
-
2024-06-26
Li, Pan2
New
[v1] RISC-V: Add testcases for vector truncate after .SAT_SUB
[v1] RISC-V: Add testcases for vector truncate after .SAT_SUB
- - - -
-
-
-
2024-06-25
Li, Pan2
New
[v2] Vect: Support truncate after .SAT_SUB pattern in zip
[v2] Vect: Support truncate after .SAT_SUB pattern in zip
- - - -
-
-
-
2024-06-24
Li, Pan2
New
[v1] Ifcvt: Add cond tree reconcile for truncated .SAT_SUB
[v1] Ifcvt: Add cond tree reconcile for truncated .SAT_SUB
- - - -
-
-
-
2024-06-21
Li, Pan2
New
[v1,8/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
[v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
- - - -
-
-
-
2024-06-19
Li, Pan2
New
[v1,7/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9
[v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
- - - -
-
-
-
2024-06-19
Li, Pan2
New
[v1,6/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8
[v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
- - - -
-
-
-
2024-06-19
Li, Pan2
New
[v1,5/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7
[v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
- - - -
-
-
-
2024-06-19
Li, Pan2
New
[v1,4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
[v1,1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
- - - -
-
-
-
2024-06-19
Li, Pan2
New
«
1
2
3
4
»