Toggle navigation
Patchwork
GNU Compiler Collection
Patches
Bundles
About this project
Login
Register
Mail settings
Show patches with
: Submitter =
Edwin Lu
| State =
Action Required
| Archived =
No
| 68 patches
Series
Submitter
State
any
Action Required
New
Under Review
Accepted
Rejected
RFC
Not Applicable
Changes Requested
Awaiting Upstream
Superseded
Deferred
Needs Review / ACK
Handled Elsewhere
Search
Archived
No
Yes
Both
Delegate
------
Nobody
jgarzik
arnd
ymano
smfrench
jlayton
tseliot
ogasawara
amitk
awhitcroft
mst
dayangkun
jwboyer
jwboyer
colinking
colinking
azummo
dwmw2
rtg
sconklin
smb
aliguori
bradf
demarchi
ms
bhundven
chbs
kengyu
kadlec
pdp
regit
jabk
laforge
laforge
tonyb
alai
zecke
zecke
__damien__
luka
luka
prafulla@marvell.com
cyrus
PeterHuewe
kiho
jow
jow
ypwong
nico
dedeckeh
dedeckeh
yousong
yousong
tomcwarren
mb
mrchuck
vineetg76
computersforpeace
Noltari
Noltari
patrick_delaunay
ee07b291
ldir
ldir
stefanct
zhouhan
carldani
blp
ffainelli
ffainelli
regXboi
bbrezillon
pravin
mkp
jpettit
mkresin
mkresin
thess
thess
fbarrat
fbarrat
phil
linville
jesse
tjaalton
esben
abrodkin
abrodkin
diproiettod
tbot
stephenfin
vriera
darball1
sammj
ajd
jogo
jogo
bhelgaas
blogic
blogic
tagr
tagr
tagr
oohal
russellb
ptomsich
agraf
joestringer
mwalle
naveen
pchotard
pepe2k
pepe2k
arj
arj
davem
davem
davem
andmur01
amitay
matttbe
pabeni
istokes
tytso
aparcar
Ansuel
goliath
martineau
danielschwierzeck
mariosix
dcaratti
hs
ovsrobot
ovsrobot
tpetazzoni
XiaoYang
mkorpershoek
aserdean
marex
khem
liwang
mmichelson
danielhb
groug
robimarko
npiggin
apritzel
pareddja
atishp
netdrv
mkubecek
stintel
stintel
jkicinski
cpitchen
maximeh
dsa
jstancek
pm215
bpf
jonhunter
shettyg
lorpie01
acelan
wigyori
wigyori
apopple
dja
alexhung
lynxis
lynxis
brgl
brgl
peda
akodanev
narmstrong
0andriy
981213
monstr
snowpatch_ozlabs
snowpatch_ozlabs
snowpatch_ozlabs
aivanov
atishp04
shemminger
blocktrron
vigneshr
mraynal
chunkeey
stewart
stewart
xypron
kabel
ukleinek
ukleinek
prom
horms
rfried
sjg
ivanhu
freenix
Jaehoon
rsalvaterra
adrianschmutzler
jacmet
hegdevasant
hegdevasant
jagan
ag
metan
akumar
ehristev
bmeng
wsa
rmilecki
rmilecki
kevery
arbab
svanheule
abelloni
rw
rw
apconole
pablo
pablo
wbx
trini
legoater
legoater
legoater
chleroy
bjonglez
ynezz
pevik
sbabic
sbabic
aik
xback
xback
richiejp
dangole
dangole
forty
anuppatel
anuppatel
next_ghost
acer
echaudron
Hauke
Hauke
benh
rgrimm
segher
pratyush
passgat
jms
jms
jms
mans0n
ruscur
jk
jk
jk
jk
Andes
jmberg
numans
festevam
ymorin
ymorin
xuyang
linusw
linusw
kubu
tambarus
matthias_bgg
conchuod
strlen
strlen
imaximets
spectrum
dceara
pbrobinson
stroese
krzk
apalos
cazzacarna
neocturne
aldot
TIENFONG
mpe
sfr
galak
ktraynor
arnout
robh
anguy11
calebccff
nbd
nbd
paulus
jm
Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
RISC-V: Remove testcase XFAIL
RISC-V: Remove testcase XFAIL
- - - -
-
-
-
2024-08-19
Edwin Lu
New
RISC-V: Fix missing abi arg in test
RISC-V: Fix missing abi arg in test
- - - -
-
-
-
2024-08-07
Edwin Lu
New
RISC-V: Add configure check for B extention support
RISC-V: Add configure check for B extention support
- - - -
-
-
-
2024-07-24
Edwin Lu
New
RISC-V: Fix testcase missing arch attribute
RISC-V: Fix testcase missing arch attribute
- - 1 -
-
-
-
2024-07-17
Edwin Lu
New
RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark
- - - -
-
-
-
2024-07-12
Edwin Lu
New
[V2,2/2] RISC-V: Update testsuite to use b
Add support for B extention
- - - -
-
-
-
2024-07-09
Edwin Lu
New
[V2,1/2] RISC-V: Add support for B standard extension
Add support for B extention
- - - -
-
-
-
2024-07-09
Edwin Lu
New
[2/2] RISC-V: Update testsuite to use b
Add support for B extention
- - - -
-
-
-
2024-07-08
Edwin Lu
New
[1/2] RISC-V: Add support for B standard extension
Add support for B extention
- - - -
-
-
-
2024-07-08
Edwin Lu
New
[V3,2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn
Fix ICE with vwsll combine on 32bit targets
- - - -
-
-
-
2024-06-17
Edwin Lu
New
[V3,1/2] RISC-V: Fix vwsll combine on rv32 targets
Fix ICE with vwsll combine on 32bit targets
- - - -
-
-
-
2024-06-17
Edwin Lu
New
[V2,2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn
Fix ICE with vwsll combine on 32bit targets
- - - -
-
-
-
2024-06-13
Edwin Lu
New
[V2,1/2] RISC-V: Fix vwsll combine on rv32 targets
Fix ICE with vwsll combine on 32bit targets
- - - -
-
-
-
2024-06-13
Edwin Lu
New
[2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn
[1/2] RISC-V: Fix vwsll combine on rv32 targets
- - - -
-
-
-
2024-06-11
Edwin Lu
New
[1/2] RISC-V: Fix vwsll combine on rv32 targets
[1/2] RISC-V: Fix vwsll combine on rv32 targets
- - - -
-
-
-
2024-06-11
Edwin Lu
New
RISC-V: Fix testcases renamed test flag options
RISC-V: Fix testcases renamed test flag options
- - - -
-
-
-
2024-05-16
Edwin Lu
New
[gcc-13,backport] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
[gcc-13,backport] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
1 - - -
-
-
-
2024-04-03
Edwin Lu
New
RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
- - - -
-
-
-
2024-03-18
Edwin Lu
New
[V2] RISC-V: Update test expectancies with recent scheduler change
[V2] RISC-V: Update test expectancies with recent scheduler change
- - - -
-
-
-
2024-03-12
Edwin Lu
New
middle-end: Fix dominator information with loop duplication PR114197
middle-end: Fix dominator information with loop duplication PR114197
- - - -
-
-
-
2024-03-01
Edwin Lu
New
RISC-V: Update test expectancies with recent scheduler change
RISC-V: Update test expectancies with recent scheduler change
- - - -
-
-
-
2024-02-23
Edwin Lu
New
[V2] RISC-V: Specify mtune and march for PR113742
[V2] RISC-V: Specify mtune and march for PR113742
- - - -
-
-
-
2024-02-20
Edwin Lu
New
[V4,5/5] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,4/5] RISC-V: Quick and simple fixes to testcases that break due to reordering
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,3/5] RISC-V: Use default cost model for insn scheduling
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,2/5] RISC-V: Add vector related pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,1/5] RISC-V: Add non-vector types to dfa pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
RISC-V: Set require-effective-target rv64 for PR113742
RISC-V: Set require-effective-target rv64 for PR113742
- - - -
-
-
-
2024-02-14
Edwin Lu
New
testsuite: Add support for scanning assembly with comparitor
testsuite: Add support for scanning assembly with comparitor
- - - -
-
-
-
2024-02-12
Edwin Lu
New
RISC-V: Add support for B standard extension
RISC-V: Add support for B standard extension
- - - -
-
-
-
2024-02-06
Edwin Lu
New
[V4,2/4] RISC-V: Add vector related pipelines
Untitled series #393042
- - - -
-
-
-
2024-01-31
Edwin Lu
New
RISC-V: Fix rvv intrinsic pragma tests dejagnu selector
RISC-V: Fix rvv intrinsic pragma tests dejagnu selector
- - 1 -
-
-
-
2024-01-29
Edwin Lu
New
[V3,4/4] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V3,3/4] RISC-V: Use default cost model for insn scheduling
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V3,2/4] RISC-V: Add vector related pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V3,1/4] RISC-V: Add non-vector types to dfa pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V2,4/4,RFC] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[V2,3/4,RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[V2,2/4,RFC] RISC-V: Add vector related reservations
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[V2,1/4,RFC] RISC-V: Add non-vector types to dfa pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[3/3,RFC] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2023-12-15
Edwin Lu
New
[2/3,RFC] RISC-V: Add vector related reservations
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2023-12-15
Edwin Lu
New
[1/3,RFC] RISC-V: Add non-vector types to pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2023-12-15
Edwin Lu
New
[V3] RISC-V: XFAIL scan dump fails for autovec PR111311
[V3] RISC-V: XFAIL scan dump fails for autovec PR111311
- - - -
-
-
-
2023-12-13
Edwin Lu
New
[V2] RISC-V: XFAIL scan dump fails for autovec PR111311
[V2] RISC-V: XFAIL scan dump fails for autovec PR111311
- - - -
-
-
-
2023-12-08
Edwin Lu
New
RISC-V: XFAIL scan dump fails for autovec PR111311
RISC-V: XFAIL scan dump fails for autovec PR111311
- - - -
-
-
-
2023-12-07
Edwin Lu
New
RISC-V: Remove xfail from ssa-fre-3.c testcase
RISC-V: Remove xfail from ssa-fre-3.c testcase
- - 1 -
-
-
-
2023-12-06
Edwin Lu
New
RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]
RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]
- - - -
-
-
-
2023-11-15
Edwin Lu
New
RISC-V: Add check for types without insn reservations
RISC-V: Add check for types without insn reservations
- - - -
-
-
-
2023-11-01
Edwin Lu
New
[RFC] Make genautomata.cc output reflect insn-attr.h expectation:
[RFC] Make genautomata.cc output reflect insn-attr.h expectation:
- - - -
-
-
-
2023-10-31
Edwin Lu
New
[RFC] RISC-V: Handle new types in scheduling descriptions
[RFC] RISC-V: Handle new types in scheduling descriptions
- - - -
-
-
-
2023-10-09
Edwin Lu
New
RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
- - - -
-
-
-
2023-09-11
Edwin Lu
New
[v2,2/5] RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-08
Edwin Lu
New
[v2,1/5] RISC-V: Update Types for Vector Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-08
Edwin Lu
New
[5/5] RISC-V: Remove Assert Protecting Types
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[4/5] RISC-V: Update Types for RISC-V Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[2/5] RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[1/5] RISC-V: Update Types for Vector Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
Add Types to Un-Typed Pic Instructions:
Add Types to Un-Typed Pic Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V Add Types to Un-Typed Thead Instructions:
RISC-V Add Types to Un-Typed Thead Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V: Add Types to Un-Typed Risc-v Instructions:
RISC-V: Add Types to Un-Typed Risc-v Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V: Add Types to Un-Typed Vector Instructions:
RISC-V: Add Types to Un-Typed Vector Instructions:
- - - -
-
-
-
2023-08-28
Edwin Lu
New
MAINTAINERS: Add myself to write after approval
MAINTAINERS: Add myself to write after approval
- - - -
-
-
-
2023-08-25
Edwin Lu
New
[V2] RISC-V: Add Types to Un-Typed Sync Instructions:
[V2] RISC-V: Add Types to Un-Typed Sync Instructions:
- - - -
-
-
-
2023-08-24
Edwin Lu
New
RISC-V: Add Types to Un-Typed Sync Instructions:
RISC-V: Add Types to Un-Typed Sync Instructions:
- - - -
-
-
-
2023-08-21
Edwin Lu
New
RISC-V: Add Types to Missing Bitmanip Instructions:
RISC-V: Add Types to Missing Bitmanip Instructions:
- - - -
-
-
-
2023-08-21
Edwin Lu
New
[V3] riscv: generate builtin macro for compilation with strict alignment:
[V3] riscv: generate builtin macro for compilation with strict alignment:
- - - -
-
-
-
2023-08-15
Edwin Lu
New