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Apply
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Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v2,1/2] MIPS: add pattern insqisi_extended and inshisi_extended
[v2,1/2] MIPS: add pattern insqisi_extended and inshisi_extended
- - - -
-
-
-
2023-12-29
YunQiang Su
New
middle-end: Fix dominators updates when peeling with multiple exits [PR113144]
middle-end: Fix dominators updates when peeling with multiple exits [PR113144]
- - - -
-
-
-
2023-12-29
Tamar Christina
New
middle-end: rejects loops with nonlinear inductions and early breaks [PR113163]
middle-end: rejects loops with nonlinear inductions and early breaks [PR113163]
- - - -
-
-
-
2023-12-29
Tamar Christina
New
[20/21] Arm: Add Advanced SIMD cbranch implementation
Untitled series #388362
- - - -
-
-
-
2023-12-29
Tamar Christina
New
AArch64 Update costing for vector conversions [PR110625]
AArch64 Update costing for vector conversions [PR110625]
- - - -
-
-
-
2023-12-29
Tamar Christina
New
[pushed] LoongArch: Fix the format of bstrins_<mode>_for_ior_mask condition (NFC)
[pushed] LoongArch: Fix the format of bstrins_<mode>_for_ior_mask condition (NFC)
- - - -
-
-
-
2023-12-29
Xi Ruoyao
New
Pushed: [PATCH v4] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with com…
Pushed: [PATCH v4] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with com…
- - - -
-
-
-
2023-12-29
Xi Ruoyao
New
[2/2] MIPS: define_attr perf_ratio in mips.md
[1/2] MIPS: add pattern insqisi_extended
- - - -
-
-
-
2023-12-29
YunQiang Su
New
[1/2] MIPS: add pattern insqisi_extended
[1/2] MIPS: add pattern insqisi_extended
- - - -
-
-
-
2023-12-29
YunQiang Su
New
Do not count unused scalar use when marking STMT_VINFO_LIVE_P [PR113091]
Do not count unused scalar use when marking STMT_VINFO_LIVE_P [PR113091]
- - - -
-
-
-
2023-12-29
Feng Xue OS
New
[committed] i386: Fix TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter [PR113133]
[committed] i386: Fix TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter [PR113133]
- - - -
-
-
-
2023-12-29
Uros Bizjak
New
[v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-26.c.
[v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-26.c.
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-21.c.
[v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-21.c.
- - - -
-
-
-
2023-12-29
chenxiaolong
New
Fix gen-vect-26.c testcase after loops with multiple exits [PR113167]
Fix gen-vect-26.c testcase after loops with multiple exits [PR113167]
- - - -
-
-
-
2023-12-29
Andrew Pinski
New
[v4,6/6] RISC-V: Add support for xtheadvector-specific intrinsics.
[v4] RISC-V: Refactor riscv-vector-builtins-bases.cc
- - - -
-
-
-
2023-12-29
joshua
New
[v4] RISC-V: Handle differences between XTheadvector and Vector
[v4] RISC-V: Handle differences between XTheadvector and Vector
- - - -
-
-
-
2023-12-29
joshua
New
[v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
[v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
- - - -
-
-
-
2023-12-29
joshua
New
[v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
[v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
- - - -
-
-
-
2023-12-29
joshua
New
[v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns.
[v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns.
- - - -
-
-
-
2023-12-29
joshua
New
[v4] RISC-V: Change csr_operand into
[v4] RISC-V: Change csr_operand into
- - - -
-
-
-
2023-12-29
joshua
New
[v4] RISC-V: Refactor riscv-vector-builtins-bases.cc
[v4] RISC-V: Refactor riscv-vector-builtins-bases.cc
- - - -
-
-
-
2023-12-29
joshua
New
[v1] LoongArch: testsuite:Add the "-ffast-math" compilation option for the file vect-fmin-3.c.
[v1] LoongArch: testsuite:Add the "-ffast-math" compilation option for the file vect-fmin-3.c.
- - - -
-
-
-
2023-12-29
chenxiaolong
New
Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
- - - -
-
-
-
2023-12-29
joshua
New
Re:Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
Re:Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
- - - -
-
-
-
2023-12-29
joshua
New
Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
- - - -
-
-
-
2023-12-29
joshua
New
[v1,8/8] LoongArch: testsuite:Modify the result check in the FMA file.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,7/8] LoongArch: testsuite:Added additional vectorization "-mlsx" compilation option.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,6/8] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,5/8] LoongArch: testsuite:Modify the test behavior in file pr60510.f.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,4/8] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,3/8] LoongArch: testsuite:Added test support for vect-{82, 83}.c.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,2/8] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12, 23}.c file.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[v1,1/8] LoongArch: testsuite:Add detection procedures supported by the target.
LoongArch:Enable testing for common
- - - -
-
-
-
2023-12-29
chenxiaolong
New
Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
Re:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
- - - -
-
-
-
2023-12-29
joshua
New
回复:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
回复:[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
- - - -
-
-
-
2023-12-29
joshua
New
[v4,6/6] RISC-V: Add support for xtheadvector-specific intrinsics.
Untitled series #388306
- - - -
-
-
-
2023-12-29
joshua
New
[v4,5/6] RISC-V: Handle differences between XTheadvector and Vector
Untitled series #388306
- - - -
-
-
-
2023-12-29
joshua
New
[v1] LoongArch: testsuite:Fix FAIL in lasx-xvstelm.c file.
[v1] LoongArch: testsuite:Fix FAIL in lasx-xvstelm.c file.
- - - -
-
-
-
2023-12-29
chenxiaolong
New
[Committed] RISC-V: Robostify testcase pr113112-1.c
[Committed] RISC-V: Robostify testcase pr113112-1.c
- - - -
-
-
-
2023-12-29
钟居哲
New
RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model
RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model
- - - -
-
-
-
2023-12-29
钟居哲
New
[v3] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine
[v3] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine
- - - -
-
-
-
2023-12-28
Xi Ruoyao
New
[middle-end] Only call targetm.truly_noop_truncation for truncations.
[middle-end] Only call targetm.truly_noop_truncation for truncations.
- - - -
-
-
-
2023-12-28
Roger Sayle
New
Improved RTL expansion of field assignments into promoted registers.
Improved RTL expansion of field assignments into promoted registers.
- - - -
-
-
-
2023-12-28
Roger Sayle
New
MIPS: Implement TARGET_INSN_COSTS
MIPS: Implement TARGET_INSN_COSTS
- - - -
-
-
-
2023-12-28
YunQiang Su
New
aarch64: fortran: Adjust vect-8.f90 for libmvec
aarch64: fortran: Adjust vect-8.f90 for libmvec
- - - -
-
-
-
2023-12-28
Szabolcs Nagy
New
[v2] LoongArch: Merge constant vector permuatation implementations.
[v2] LoongArch: Merge constant vector permuatation implementations.
- - - -
-
-
-
2023-12-28
Li Wei
New
[committed] i386: Cleanup ix86_expand_{unary|binary}_operator issues
[committed] i386: Cleanup ix86_expand_{unary|binary}_operator issues
- - - -
-
-
-
2023-12-28
Uros Bizjak
New
[v1] LoongArch: Merge constant vector permuatation implementations.
[v1] LoongArch: Merge constant vector permuatation implementations.
- - - -
-
-
-
2023-12-28
Li Wei
New
[Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes
[Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes
- - - -
-
-
-
2023-12-28
钟居哲
New
[C] C: Fix type compatibility for structs with variable sized fields.
[C] C: Fix type compatibility for structs with variable sized fields.
- - - -
-
-
-
2023-12-27
Martin Uecker
New
aarch64: add 'AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA'
aarch64: add 'AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA'
- - - -
-
-
-
2023-12-27
Di Zhao OS
New
[2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro instr…
When cmodel=extreme, add macro support and only
- - - -
-
-
-
2023-12-27
Lulu Cheng
New
[1/2] LoongArch: Add the macro implementation of mcmodel=extreme.
When cmodel=extreme, add macro support and only
- - - -
-
-
-
2023-12-27
Lulu Cheng
New
[Committed] RISC-V: Make known NITERS loop be aware of dynamic lmul cost model liveness information
[Committed] RISC-V: Make known NITERS loop be aware of dynamic lmul cost model liveness information
- - - -
-
-
-
2023-12-27
钟居哲
New
[V2] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31]
[V2] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31]
- - - -
-
-
-
2023-12-27
钟居哲
New
RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31]
RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31]
- - - -
-
-
-
2023-12-27
钟居哲
New
LoongArch: Fix infinite secondary reloading of FCCmode [PR113148]
LoongArch: Fix infinite secondary reloading of FCCmode [PR113148]
- - - -
-
-
-
2023-12-26
Xi Ruoyao
New
[Committed] RISC-V: Fix typo
[Committed] RISC-V: Fix typo
- - - -
-
-
-
2023-12-26
钟居哲
New
[v2] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
[v2] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
- - - -
-
-
-
2023-12-26
Li, Pan2
New
[Committed] RISC-V: Some minior tweak on dynamic LMUL cost model
[Committed] RISC-V: Some minior tweak on dynamic LMUL cost model
- - - -
-
-
-
2023-12-26
钟居哲
New
[V3,3/3] RISC-V: Add C intrinsic for Scalar Bitmanip Extension
[V3,1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites
- - - -
-
-
-
2023-12-26
Liao Shihua
New
[V3,2/3] RISC-V: Add C intrinsic for Scalar Crypto Extension
[V3,1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites
- - - -
-
-
-
2023-12-26
Liao Shihua
New
[V3,1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites
[V3,1/3] RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function testsuites
- - - -
-
-
-
2023-12-26
Liao Shihua
New
[v2] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine
[v2] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine
- - - -
-
-
-
2023-12-25
Xi Ruoyao
New
[committed] middle-end: explicitly initialize vec_stmts [PR113132]
[committed] middle-end: explicitly initialize vec_stmts [PR113132]
- - - -
-
-
-
2023-12-25
Tamar Christina
New
RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo
RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo
- - - -
-
-
-
2023-12-25
钟居哲
New
RISC-V: Fix misaligned stack offset for interrupt function
RISC-V: Fix misaligned stack offset for interrupt function
- - - -
-
-
-
2023-12-25
Kito Cheng
New
[v4,4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
Untitled series #388000
- - - -
-
-
-
2023-12-25
joshua
New
回复:[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
回复:[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
- - - -
-
-
-
2023-12-25
joshua
New
[v4,6/6] RISC-V: Add support for xtheadvector-specific intrinsics.
Untitled series #387994
- - - -
-
-
-
2023-12-25
joshua
New
[v4,5/6] RISC-V: Handle differences between XTheadvector and Vector
Untitled series #387994
- - - -
-
-
-
2023-12-25
joshua
New
[v4,4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.
Untitled series #387994
- - - -
-
-
-
2023-12-25
joshua
New
[Committed] RISC-V: Add one more ASM check in PR113112-1.c
[Committed] RISC-V: Add one more ASM check in PR113112-1.c
- - - -
-
-
-
2023-12-25
钟居哲
New
[COMMITTED] match: Improve `(a != b) ? (a + b) : (2 * a)` pattern [PR19832]
[COMMITTED] match: Improve `(a != b) ? (a + b) : (2 * a)` pattern [PR19832]
- - - -
-
-
-
2023-12-25
Andrew Pinski
New
[v1] LoongArch: Fixed bug in *bstrins_<mode>_for_ior_mask template.
[v1] LoongArch: Fixed bug in *bstrins_<mode>_for_ior_mask template.
- - - -
-
-
-
2023-12-25
Li Wei
New
[testsuite] : Add more pragma novector to new tests
[testsuite] : Add more pragma novector to new tests
- - - -
-
-
-
2023-12-24
Tamar Christina
New
[committed] hppa: Fix pr110279-1.c on hppa
[committed] hppa: Fix pr110279-1.c on hppa
- - - -
-
-
-
2023-12-24
John David Anglin
New
[v2] LoongArch: Expand left rotate to right rotate with negated amount
[v2] LoongArch: Expand left rotate to right rotate with negated amount
- - - -
-
-
-
2023-12-24
Xi Ruoyao
New
[committed] CRIS: Fix PR middle-end/113109; "throw" failing
[committed] CRIS: Fix PR middle-end/113109; "throw" failing
- - - -
-
-
-
2023-12-24
Hans-Peter Nilsson
New
[ARC] Table-driven ashlsi implementation for better code/rtx_costs.
[ARC] Table-driven ashlsi implementation for better code/rtx_costs.
- - - -
-
-
-
2023-12-23
Roger Sayle
New
[v2] libstdc++: Use _GLIBCXX_USE_BUILTIN_TRAIT
[v2] libstdc++: Use _GLIBCXX_USE_BUILTIN_TRAIT
- - 1 -
-
-
-
2023-12-23
Ken Matsui
New
[v2,8/8] libstdc++: Optimize std::is_unbounded_array compilation performance
Optimize more type traits
- - - -
-
-
-
2023-12-23
Ken Matsui
New
[v2,7/8] c++: Implement __is_unbounded_array built-in trait
Optimize more type traits
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2023-12-23
Ken Matsui
New
[v2,6/8] libstdc++: Optimize std::is_pointer compilation performance
Optimize more type traits
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2023-12-23
Ken Matsui
New
[v2,5/8] c++: Implement __is_pointer built-in trait
Optimize more type traits
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2023-12-23
Ken Matsui
New
[v2,4/8] libstdc++: Optimize std::is_volatile compilation performance
Optimize more type traits
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2023-12-23
Ken Matsui
New
[v2,3/8] c++: Implement __is_volatile built-in trait
Optimize more type traits
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2023-12-23
Ken Matsui
New
[v2,2/8] libstdc++: Optimize std::is_const compilation performance
Optimize more type traits
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2023-12-23
Ken Matsui
New
[v2,1/8] c++: Implement __is_const built-in trait
Optimize more type traits
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2023-12-23
Ken Matsui
New
[2/8] libstdc++: Optimize std::is_const compilation performance
Optimize more type traits
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2023-12-23
Ken Matsui
New
[1/8] c++: Implement __is_const built-in trait
Optimize more type traits
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2023-12-23
Ken Matsui
New
reassoc vs uninitialized variable {PR112581]
reassoc vs uninitialized variable {PR112581]
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2023-12-23
Andrew Pinski
New
[v2] RISC-V: XFail the signbit-5 run test for RVV
[v2] RISC-V: XFail the signbit-5 run test for RVV
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2023-12-23
Li, Pan2
New
[v1] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
[v1] RISC-V: XFAIL pr30957-1.c when loop vectorized with variable factor
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2023-12-23
Li, Pan2
New
[v3] EXPR: Emit an truncate if 31+ bits polluted for SImode
[v3] EXPR: Emit an truncate if 31+ bits polluted for SImode
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2023-12-23
YunQiang Su
New
[commit,v3,2/2] MIPS: Don't add nan2008 option for -mtune=native
[commit,v3,1/2] MIPS: Put the ret to the end of args of reconcat [PR112759]
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2023-12-23
YunQiang Su
New
[commit,v3,1/2] MIPS: Put the ret to the end of args of reconcat [PR112759]
[commit,v3,1/2] MIPS: Put the ret to the end of args of reconcat [PR112759]
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2023-12-23
YunQiang Su
New
[Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis
[Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis
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2023-12-22
钟居哲
New
[COMMITTED] robots.txt: Disallow a few more bugzilla queries
[COMMITTED] robots.txt: Disallow a few more bugzilla queries
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2023-12-22
Mark Wielaard
New
RISC-V: RVV: add toggle to control vsetvl pass behavior
RISC-V: RVV: add toggle to control vsetvl pass behavior
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2023-12-22
Vineet Gupta
New
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