Show patches with: Submitter = Vineet Gupta       |    State = Action Required       |    Archived = No       |   94 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
sched1: debug/model: dump predecessor list and BB num [NFC] sched1: debug/model: dump predecessor list and BB num [NFC] - - - - --- 2024-11-05 Vineet Gupta New
[v2] sched1: parameterize pressure scheduling spilling agressiveness [PR/114729] [v2] sched1: parameterize pressure scheduling spilling agressiveness [PR/114729] - - - - --- 2024-11-05 Vineet Gupta New
[COMMITTED] RISC-V: fix const interleaved stepped vector with a scalar pattern [COMMITTED] RISC-V: fix const interleaved stepped vector with a scalar pattern - - - 1 --- 2024-10-31 Vineet Gupta New
RISC-V: fix const interleaved stepped vector with a scalar pattern RISC-V: fix const interleaved stepped vector with a scalar pattern - - - - --- 2024-10-30 Vineet Gupta New
[4/4] sched1: model: ICE on infinite loops in predecessor promotion (Not for Merge) sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
[3/4] sched1: model: only promote true dependecies in predecessor promotion sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
[2/4] RISC-V: Implement TARGET_SCHED_PRESSURE_PREFER_NARROW [PR/114729] sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
[1/4] sched1: hookize pressure scheduling spilling agressiveness sched1 improvements - - - - --- 2024-10-20 Vineet Gupta New
RFC model schedule tweak (was Re: sched1 pathology on RISC-V : PR/114729) RFC model schedule tweak (was Re: sched1 pathology on RISC-V : PR/114729) - - - - --- 2024-09-10 Vineet Gupta New
[COMMITTED] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [COMMITTED] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - 1 --- 2024-08-15 Vineet Gupta New
[RESEND,v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [RESEND,v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-08-15 Vineet Gupta New
[COMMITTED] RISC-V: Fix snafu in SI mode splitters patch [COMMITTED] RISC-V: Fix snafu in SI mode splitters patch - - - - --- 2024-07-23 Vineet Gupta New
[v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [v5] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-07-13 Vineet Gupta New
[v4] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [v4] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-07-13 Vineet Gupta New
[v3] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins [v3] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins - - - - --- 2024-07-12 Vineet Gupta New
[v2] RISC-V: use fclass insns to implement isfinite and isnormal builtins [v2] RISC-V: use fclass insns to implement isfinite and isnormal builtins - - - - --- 2024-07-01 Vineet Gupta New
RISC-V: use fclass insns to implement isfinite and isnormal builtins RISC-V: use fclass insns to implement isfinite and isnormal builtins - - - - --- 2024-06-29 Vineet Gupta New
[COMMITTED] RISC-V: avoid LUI based const mat in alloca epilogue expansion [COMMITTED] RISC-V: avoid LUI based const mat in alloca epilogue expansion - - - 1 --- 2024-05-21 Vineet Gupta New
[COMMITTED] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] [COMMITTED] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] - - - 1 --- 2024-05-21 Vineet Gupta New
[v3,2/2] RISC-V: avoid LUI based const mat in alloca epilogue expansion [v3,1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] - - - - --- 2024-05-20 Vineet Gupta New
[v3,1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] [v3,1/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] - - - - --- 2024-05-20 Vineet Gupta New
RISC-V: propgue/epilogue expansion code minor changes [NFC] RISC-V: propgue/epilogue expansion code minor changes [NFC] - - - - --- 2024-05-15 Vineet Gupta New
[COMMITTED] RISC-V: avoid LUI based const materialization ... [part of PR/106265] [COMMITTED] RISC-V: avoid LUI based const materialization ... [part of PR/106265] - - - 1 --- 2024-05-14 Vineet Gupta New
[v2,2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-05-13 Vineet Gupta New
[v2,1/2] RISC-V: avoid LUI based const materialization ... [part of PR/106265] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-05-13 Vineet Gupta New
[Committed,2/2] RISC-V: miscll comment fixes [NFC] [Committed,1/2] docs: rtl: document GET_MODE_INNER - - - - --- 2024-05-03 Vineet Gupta New
[Committed,1/2] docs: rtl: document GET_MODE_INNER [Committed,1/2] docs: rtl: document GET_MODE_INNER - - - - --- 2024-05-03 Vineet Gupta New
[v2,1/3] docs: rtl: document GET_MODE_INNER [v2,1/3] docs: rtl: document GET_MODE_INNER - - - - --- 2024-05-02 Vineet Gupta New
[3/3] combine: initialize a local var Miscll fixlets - - - - --- 2024-05-02 Vineet Gupta New
[2/3] RISC-V: miscll comment fixes [NFC] Miscll fixlets - - - - --- 2024-05-02 Vineet Gupta New
[1/3] docs: rtl: document GET_MODE_INNER Miscll fixlets - - - - --- 2024-05-02 Vineet Gupta New
[COMMITTED] RISC-V: testsuite: ensure vtype is call clobbered [COMMITTED] RISC-V: testsuite: ensure vtype is call clobbered - - - - --- 2024-03-28 Vineet Gupta New
RISC-V: testsuite: ensure vtype is call clobbered RISC-V: testsuite: ensure vtype is call clobbered - - - - --- 2024-03-27 Vineet Gupta New
[gcc-15,3/3] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-03-16 Vineet Gupta New
[gcc-15,2/3] RISC-V: avoid LUI based const mat: keep stack offsets aligned RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-03-16 Vineet Gupta New
[gcc-15,1/3] RISC-V: avoid LUI based const materialization ... [part of PR/106265] RISC-V improve stack/array access by constant mat tweak - - - - --- 2024-03-16 Vineet Gupta New
[COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2024-01-17 Vineet Gupta New
[COMITTED,2/2] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2024-01-17 Vineet Gupta New
RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] - - - - --- 2024-01-16 Vineet Gupta New
[v2] RISC-V: RVV: add toggle to control vsetvl pass behavior [v2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2024-01-16 Vineet Gupta New
RISC-V: RVV: add toggle to control vsetvl pass behavior RISC-V: RVV: add toggle to control vsetvl pass behavior - - - - --- 2023-12-22 Vineet Gupta New
[Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] [Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - 1 - - --- 2023-11-15 Vineet Gupta New
[Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - 1 --- 2023-11-15 Vineet Gupta New
RISC-V: fix vsetvli pass testsuite failure [PR/112447] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - 2 - - --- 2023-11-15 Vineet Gupta New
[RESEND,v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [RESEND,v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - - --- 2023-11-15 Vineet Gupta New
[[Committed] ] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls [[Committed] ] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - 1 - 1 --- 2023-11-01 Vineet Gupta New
RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - - - 1 --- 2023-10-31 Vineet Gupta New
[v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - 1 --- 2023-10-30 Vineet Gupta New
[v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - - --- 2023-10-30 Vineet Gupta New
[RFC] RISC-V: elide sign extend when expanding cmp_and_jump [RFC] RISC-V: elide sign extend when expanding cmp_and_jump - - - - --- 2023-10-25 Vineet Gupta New
[COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output [COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output - - - - --- 2023-10-17 Vineet Gupta New
[v2] RISC-V/testsuite/pr111466.c: update test and expected output [v2] RISC-V/testsuite/pr111466.c: update test and expected output - - - - --- 2023-10-17 Vineet Gupta New
RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W - - - - --- 2023-10-17 Vineet Gupta New
[COMMITTED] RISC-V/testsuite: add a default march (lacking zfa) to some fp tests [COMMITTED] RISC-V/testsuite: add a default march (lacking zfa) to some fp tests - - - - --- 2023-10-16 Vineet Gupta New
RISC-V/testsuite: add a default march (lacking zfa) to some fp tests RISC-V/testsuite: add a default march (lacking zfa) to some fp tests - - - - --- 2023-10-15 Vineet Gupta New
[COMMITTED] RISC-V: const: hide mvconst splitter from IRA [COMMITTED] RISC-V: const: hide mvconst splitter from IRA - - - - --- 2023-10-06 Vineet Gupta New
[v2] RISC-V: const: hide mvconst splitter from IRA [v2] RISC-V: const: hide mvconst splitter from IRA - - - - --- 2023-10-06 Vineet Gupta New
[RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466] [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466] - - - - --- 2023-09-28 Vineet Gupta New
[Committed] RISC-V: zicond: Fix opt2 pattern [Committed] RISC-V: zicond: Fix opt2 pattern - 1 - - --- 2023-09-05 Vineet Gupta New
[v2] RISC-V: zicond: Fix opt2 pattern [v2] RISC-V: zicond: Fix opt2 pattern - 1 - - --- 2023-09-01 Vineet Gupta New
RISC-V: zicond: remove bogus opt2 pattern RISC-V: zicond: remove bogus opt2 pattern - 1 - - --- 2023-08-30 Vineet Gupta New
[Committed] RISC-V: Enable Hoist to GCSE simple constants [Committed] RISC-V: Enable Hoist to GCSE simple constants - - - - --- 2023-08-25 Vineet Gupta New
[v2] RISC-V: Enable Hoist to GCSE simple constants [v2] RISC-V: Enable Hoist to GCSE simple constants - - - - --- 2023-08-25 Vineet Gupta New
[Committed] RISC-V: output Autovec params explicitly in --help ... [Committed] RISC-V: output Autovec params explicitly in --help ... - - - - --- 2023-08-22 Vineet Gupta New
RISC-V: output Autovec params explicitly in --help ... RISC-V: output Autovec params explicitly in --help ... - - - - --- 2023-08-22 Vineet Gupta New
RISC-V: Enable Hoist to GCSE simple constants RISC-V: Enable Hoist to GCSE simple constants - - - - --- 2023-08-10 Vineet Gupta New
[Committed] RISC-V: optim const DF +0.0 store to mem [PR/110748] [Committed] RISC-V: optim const DF +0.0 store to mem [PR/110748] - 1 - - --- 2023-07-22 Vineet Gupta New
[v2] RISC-V: optim const DF +0.0 store to mem [PR/110748] [v2] RISC-V: optim const DF +0.0 store to mem [PR/110748] - 1 - - --- 2023-07-21 Vineet Gupta New
RISC-V: optim const DF +0.0 store to mem [PR/110748] RISC-V: optim const DF +0.0 store to mem [PR/110748] - - 1 - --- 2023-07-21 Vineet Gupta New
RISC-V: improve codegen for repeating large constants [3] RISC-V: improve codegen for repeating large constants [3] - - - - --- 2023-06-30 Vineet Gupta New
[Committed] testsuite: print any leaking torture options for debugging [Committed] testsuite: print any leaking torture options for debugging - - - - --- 2023-06-01 Vineet Gupta New
[Committed] testsuite: Unbork multilib setups using -march flags (RISC-V) [Committed] testsuite: Unbork multilib setups using -march flags (RISC-V) - - - - --- 2023-06-01 Vineet Gupta New
[3/3] testsuite: print any leaking torture options for debugging Unbork testsuite for multlib setups - - - - --- 2023-05-31 Vineet Gupta New
[2/3] RISC-V: Add missing torture-init and torture-finish for rvv.exp Unbork testsuite for multlib setups - - - - --- 2023-05-31 Vineet Gupta New
[1/3] testsuite: Unbork multilib testing on RISC-V (and any target really) Unbork testsuite for multlib setups - - - - --- 2023-05-31 Vineet Gupta New
RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] - - - - --- 2023-05-18 Vineet Gupta New
MAINTAINERS: add Vineet Gupta to write after approval MAINTAINERS: add Vineet Gupta to write after approval 1 - - - --- 2023-04-20 Vineet Gupta New
[v2] expansion: make layout of x_shift*cost[][][] more efficient [v2] expansion: make layout of x_shift*cost[][][] more efficient - - - - --- 2023-04-18 Vineet Gupta New
expansion: make layout of x_shift*cost[][][] more efficient expansion: make layout of x_shift*cost[][][] more efficient - - - - --- 2023-04-18 Vineet Gupta New
[v2] riscv: relax splitter restrictions for creating pseudos [v2] riscv: relax splitter restrictions for creating pseudos - - - - --- 2023-04-18 Vineet Gupta New
riscv: relax splitter restrictions for creating pseudos riscv: relax splitter restrictions for creating pseudos - - - - --- 2023-04-18 Vineet Gupta New
RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] - - 1 - --- 2023-03-01 Vineet Gupta New
riscv: generate builtin macro for compilation with strict alignment riscv: generate builtin macro for compilation with strict alignment - - - - --- 2023-01-17 Vineet Gupta New
RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand - - - - --- 2022-09-02 Vineet Gupta New
[v3] RISC-V: remove deprecate pic code model macro [v3] RISC-V: remove deprecate pic code model macro - - - - --- 2022-09-02 Vineet Gupta New
[v2] RISC-V: remove deprecate pic code model macro [v2] RISC-V: remove deprecate pic code model macro - - - - --- 2022-09-02 Vineet Gupta New
[2/2] RISC-V: remove CM_PIC as it doesn't do much PIC cleanup - - - - --- 2022-08-30 Vineet Gupta New
[1/2] RISC-V: remove deprecate pic code model macro PIC cleanup - - - - --- 2022-08-30 Vineet Gupta New
testsuite: constraint some of fp tests to hard_float testsuite: constraint some of fp tests to hard_float - - - - --- 2022-05-30 Vineet Gupta New
[v3] RISC-V/testsuite: constraint some of tests to hard_float [v3] RISC-V/testsuite: constraint some of tests to hard_float - - - - --- 2022-05-27 Vineet Gupta New
[v2] RISC-V/testsuite: constraint some of tests to hard_float [v2] RISC-V/testsuite: constraint some of tests to hard_float - - - - --- 2022-05-27 Vineet Gupta New
RISC-V/testsuite: constraint some of tests to hard_float RISC-V/testsuite: constraint some of tests to hard_float - - - - --- 2022-05-27 Vineet Gupta New
[PR/target,105666] RISC-V: Inhibit FP <--> int register moves via tune param [PR/target,105666] RISC-V: Inhibit FP <--> int register moves via tune param - - - - --- 2022-05-23 Vineet Gupta New
RISC-V: Enable TARGET_SUPPORTS_WIDE_INT RISC-V: Enable TARGET_SUPPORTS_WIDE_INT - - 1 - --- 2022-02-07 Vineet Gupta New