| Message ID | a6f7e1a4b20ff7eb199e94ca0c8aa2e6794ce5b2.1723172696.git.haibo1.xu@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] tests/acpi: Add empty ACPI SRAT data file for RISC-V | expand |
On Fri, Aug 09, 2024 at 11:09:48AM +0800, Haibo Xu wrote: > Add ACPI SRAT table test case for RISC-V when NUMA was enabled. > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com> > --- > tests/qtest/bios-tables-test.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c > index 36e5c0adde..e79f3a03df 100644 > --- a/tests/qtest/bios-tables-test.c > +++ b/tests/qtest/bios-tables-test.c > @@ -1706,6 +1706,32 @@ static void test_acpi_microvm_ioapic2_tcg(void) > free_test_data(&data); > } > > +static void test_acpi_riscv64_virt_tcg_numamem(void) > +{ > + test_data data = { > + .machine = "virt", > + .arch = "riscv64", > + .tcg_only = true, > + .uefi_fl1 = "pc-bios/edk2-riscv-code.fd", > + .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd", > + .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2", > + .ram_start = 0x80000000ULL, > + .scan_len = 128ULL * 1024 * 1024, > + }; > + > + data.variant = ".numamem"; > + /* > + * RHCT will have ISA string encoded. To reduce the effort > + * of updating expected AML file for any new default ISA extension, > + * use the profile rva22s64. > + */ > + test_acpi_one(" -cpu rva22s64" > + " -object memory-backend-ram,id=ram0,size=128M" > + " -numa node,memdev=ram0", > + &data); > + free_test_data(&data); > +} > + > static void test_acpi_aarch64_virt_tcg_numamem(void) > { > test_data data = { > @@ -2466,6 +2492,8 @@ int main(int argc, char *argv[]) > } else if (strcmp(arch, "riscv64") == 0) { > if (has_tcg && qtest_has_device("virtio-blk-pci")) { > qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg); > + qtest_add_func("acpi/virt/numamem", > + test_acpi_riscv64_virt_tcg_numamem); Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Thanks, Sunil
On Fri, Aug 9, 2024 at 12:50 PM Haibo Xu <haibo1.xu@intel.com> wrote: > > Add ACPI SRAT table test case for RISC-V when NUMA was enabled. > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tests/qtest/bios-tables-test.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c > index 36e5c0adde..e79f3a03df 100644 > --- a/tests/qtest/bios-tables-test.c > +++ b/tests/qtest/bios-tables-test.c > @@ -1706,6 +1706,32 @@ static void test_acpi_microvm_ioapic2_tcg(void) > free_test_data(&data); > } > > +static void test_acpi_riscv64_virt_tcg_numamem(void) > +{ > + test_data data = { > + .machine = "virt", > + .arch = "riscv64", > + .tcg_only = true, > + .uefi_fl1 = "pc-bios/edk2-riscv-code.fd", > + .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd", > + .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2", > + .ram_start = 0x80000000ULL, > + .scan_len = 128ULL * 1024 * 1024, > + }; > + > + data.variant = ".numamem"; > + /* > + * RHCT will have ISA string encoded. To reduce the effort > + * of updating expected AML file for any new default ISA extension, > + * use the profile rva22s64. > + */ > + test_acpi_one(" -cpu rva22s64" > + " -object memory-backend-ram,id=ram0,size=128M" > + " -numa node,memdev=ram0", > + &data); > + free_test_data(&data); > +} > + > static void test_acpi_aarch64_virt_tcg_numamem(void) > { > test_data data = { > @@ -2466,6 +2492,8 @@ int main(int argc, char *argv[]) > } else if (strcmp(arch, "riscv64") == 0) { > if (has_tcg && qtest_has_device("virtio-blk-pci")) { > qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg); > + qtest_add_func("acpi/virt/numamem", > + test_acpi_riscv64_virt_tcg_numamem); > } > } > ret = g_test_run(); > -- > 2.34.1 > >
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 36e5c0adde..e79f3a03df 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1706,6 +1706,32 @@ static void test_acpi_microvm_ioapic2_tcg(void) free_test_data(&data); } +static void test_acpi_riscv64_virt_tcg_numamem(void) +{ + test_data data = { + .machine = "virt", + .arch = "riscv64", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-riscv-code.fd", + .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2", + .ram_start = 0x80000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + data.variant = ".numamem"; + /* + * RHCT will have ISA string encoded. To reduce the effort + * of updating expected AML file for any new default ISA extension, + * use the profile rva22s64. + */ + test_acpi_one(" -cpu rva22s64" + " -object memory-backend-ram,id=ram0,size=128M" + " -numa node,memdev=ram0", + &data); + free_test_data(&data); +} + static void test_acpi_aarch64_virt_tcg_numamem(void) { test_data data = { @@ -2466,6 +2492,8 @@ int main(int argc, char *argv[]) } else if (strcmp(arch, "riscv64") == 0) { if (has_tcg && qtest_has_device("virtio-blk-pci")) { qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg); + qtest_add_func("acpi/virt/numamem", + test_acpi_riscv64_virt_tcg_numamem); } } ret = g_test_run();
Add ACPI SRAT table test case for RISC-V when NUMA was enabled. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> --- tests/qtest/bios-tables-test.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)