| Message ID | 794f7476c911de3bc459eb188c181a4119e10997.1652435208.git.research_trasio@irq.a4lg.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Make property names lowercase and add capitalized aliases | expand |
On Fri, May 13, 2022 at 7:47 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Many properties for extension names are just in lowercase. On the other > hand, following extension properties and "Counters" are capitalized. > > - Zifencei > - Zicsr > - Zfh > - Zfhmin > - Zve32f > - Zve64f > > This commit chooses lowercase as primary property names but keeps > capitalized names as aliases for compatibility. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > --- > target/riscv/cpu.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ccacdee215..16227a1ac5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -822,17 +822,26 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), > - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), > + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), > + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), > + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), > + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > + /* Capitalized aliases */ > + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool), > + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool), > + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), > + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), > + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool), > + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool), > + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool), Cool! I think we should add a comment here saying not to do this for anything new. Also, it's probably worth adding a deprecation note about the capital names, then we can remove them in the future. Alistair > + > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > -- > 2.34.1 >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..16227a1ac5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -822,17 +822,26 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + /* Capitalized aliases */ + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool), + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool), + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool), + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool), + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool), + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
Many properties for extension names are just in lowercase. On the other hand, following extension properties and "Counters" are capitalized. - Zifencei - Zicsr - Zfh - Zfhmin - Zve32f - Zve64f This commit chooses lowercase as primary property names but keeps capitalized names as aliases for compatibility. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> --- target/riscv/cpu.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-)