diff mbox

[v8,6/8] STM32F205: Connect the ADC devices

Message ID 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me
State New
Headers show

Commit Message

Alistair Francis Sept. 24, 2016, 7:20 p.m. UTC 
Connect the ADC devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
---
V7:
 - Create the new ADC device
V5:
 - Use the new irq ORing function
V4:
 - Connect all the interrupt lines correctly
V2:
 - Fix up the device/devices commit message

 hw/arm/stm32f205_soc.c         | 35 +++++++++++++++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  6 ++++++
 2 files changed, 41 insertions(+)

Comments

Peter Maydell Sept. 29, 2016, 11:59 p.m. UTC | #1 
On 24 September 2016 at 12:20, Alistair Francis <alistair23@gmail.com> wrote:
> Connect the ADC devices to the STM32F205 SoC.
>
> Signed-off-by: Alistair Francis <alistair@alistair23.me>
> ---
>
>  #define FLASH_BASE_ADDRESS 0x08000000
>  #define FLASH_SIZE (1024 * 1024)
> @@ -52,6 +55,9 @@ typedef struct STM32F205State {
>      STM32F2XXSyscfgState syscfg;
>      STM32F2XXUsartState usart[STM_NUM_USARTS];
>      STM32F2XXTimerState timer[STM_NUM_TIMERS];
> +    STM32F2XXADCState adc[STM_NUM_ADCS];
> +
> +    qemu_or_irq *adc_irqs;

Seems mildly inconsistent that all the other devices
"owned" by this SoC are embedded in the struct but this
one is a pointer (and so initialized via object_new()
rather than object_initialized()).

That's not a big deal though, so I've applied this
series to target-arm.next; you can change the above
in a followup patch, or not, as you choose.

>  } STM32F205State;
>
>  #endif
> --
> 2.7.4

thanks
-- PMM
Alistair Francis Sept. 30, 2016, 12:44 a.m. UTC | #2 
On Thu, Sep 29, 2016 at 4:59 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 24 September 2016 at 12:20, Alistair Francis <alistair23@gmail.com> wrote:
>> Connect the ADC devices to the STM32F205 SoC.
>>
>> Signed-off-by: Alistair Francis <alistair@alistair23.me>
>> ---
>>
>>  #define FLASH_BASE_ADDRESS 0x08000000
>>  #define FLASH_SIZE (1024 * 1024)
>> @@ -52,6 +55,9 @@ typedef struct STM32F205State {
>>      STM32F2XXSyscfgState syscfg;
>>      STM32F2XXUsartState usart[STM_NUM_USARTS];
>>      STM32F2XXTimerState timer[STM_NUM_TIMERS];
>> +    STM32F2XXADCState adc[STM_NUM_ADCS];
>> +
>> +    qemu_or_irq *adc_irqs;
>
> Seems mildly inconsistent that all the other devices
> "owned" by this SoC are embedded in the struct but this
> one is a pointer (and so initialized via object_new()
> rather than object_initialized()).
>
> That's not a big deal though, so I've applied this
> series to target-arm.next; you can change the above
> in a followup patch, or not, as you choose.

Good point, I didn't really think of it like that.

I don't mind it this way, hopefully I will set up another patch series
and I'll update it then if need be.

Thanks,

Alistair

>
>>  } STM32F205State;
>>
>>  #endif
>> --
>> 2.7.4
>
> thanks
> -- PMM
diff mbox

Patch

diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 5b6fa3b..2feddc3 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -34,9 +34,12 @@  static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+    0x40012200 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
 
 static void stm32f205_soc_initfn(Object *obj)
 {
@@ -57,6 +60,14 @@  static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_TIMER);
         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
     }
+
+    s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        object_initialize(&s->adc[i], sizeof(s->adc[i]),
+                          TYPE_STM32F2XX_ADC);
+        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -132,6 +143,30 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
     }
+
+    /* ADC 1 to 3 */
+    object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
+                            "num-lines", &err);
+    object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
+                          qdev_get_gpio_in(nvic, ADC_IRQ));
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+        sysbus_connect_irq(busdev, 0,
+                           qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
+    }
 }
 
 static Property stm32f205_soc_properties[] = {
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 779b5da..1adf824 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -28,6 +28,8 @@ 
 #include "hw/misc/stm32f2xx_syscfg.h"
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/adc/stm32f2xx_adc.h"
+#include "hw/or-irq.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \
@@ -35,6 +37,7 @@ 
 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)
@@ -52,6 +55,9 @@  typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXADCState adc[STM_NUM_ADCS];
+
+    qemu_or_irq *adc_irqs;
 } STM32F205State;
 
 #endif