| Message ID | 20240723-counter_delegation-v2-8-c4170a5348ca@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Counter delegation ISA extension support | expand |
On Wed, Jul 24, 2024 at 9:33 AM Atish Patra <atishp@rivosinc.com> wrote: > > Add configuration options so that they can be enabled/disabld from > qemu commandline. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ac2dce734d80..1731dc461376 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1477,6 +1477,10 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), > + MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false), > + MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), > + MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), > + MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac2dce734d80..1731dc461376 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1477,6 +1477,10 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), + MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false), + MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), + MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), + MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
Add configuration options so that they can be enabled/disabld from qemu commandline. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+)