diff mbox series

[PULL,03/32] target/riscv: zvbb implies zvkb

Message ID	20240627100053.150937-4-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jerry Zhang Jian <jerry.zhangjian@sifive.com>, Frank Chang <frank.chang@sifive.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 03/32] target/riscv: zvbb implies zvkb Date: Thu, 27 Jun 2024 20:00:24 +1000 Message-ID: <20240627100053.150937-4-alistair.francis@wdc.com> In-Reply-To: <20240627100053.150937-1-alistair.francis@wdc.com> References: <20240627100053.150937-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=alistair23@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/32] target/riscv: Extend virtual irq csrs masks to be 64 bit wide. \| expand [PULL,01/32] target/riscv: Extend virtual irq csrs masks to be 64 bit wide. [PULL,02/32] target/riscv: Move Guest irqs out of the core local irqs range. [PULL,03/32] target/riscv: zvbb implies zvkb [PULL,04/32] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic() [PULL,05/32] hw/riscv/virt.c: add aplic nodename helper [PULL,06/32] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller' [PULL,07/32] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible' [PULL,08/32] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation' [PULL,09/32] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller' [PULL,10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible' [PULL,11/32] hw/riscv/virt.c: imsics DT: add '#msi-cells' [PULL,12/32] target/riscv/kvm: add software breakpoints support [PULL,13/32] target/riscv/kvm: handle the exit with debug reason [PULL,14/32] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG [PULL,15/32] target/riscv: Reuse the conversion function of priv_spec [PULL,16/32] target/riscv: Define macros and variables for ss1p13 [PULL,17/32] target/riscv: Add 'P1P13' bit in SMSTATEEN0 [PULL,18/32] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 [PULL,19/32] target/riscv: Reserve exception codes for sw-check and hw-err [PULL,20/32] target/riscv: Support the version for ss1p13 [PULL,21/32] hw/riscv/virt.c: Make block devices default to virtio [PULL,22/32] target/riscv: Fix froundnx.h nanbox check [PULL,23/32] target/riscv: fix instructions count handling in icount mode [PULL,24/32] target/riscv: Introduce extension implied rules definition [PULL,25/32] target/riscv: Introduce extension implied rule helpers [PULL,26/32] target/riscv: Add MISA extension implied rules [PULL,27/32] target/riscv: Add multi extension implied rules [PULL,28/32] target/riscv: Add Zc extension implied rule [PULL,29/32] target/riscv: Remove extension auto-update check statements [PULL,30/32] target/riscv: Add functions for common matching conditions of trigger [PULL,31/32] target/riscv: Apply modularized matching conditions for watchpoint [PULL,32/32] target/riscv: Apply modularized matching conditions for icount trigger

Commit Message

Alistair Francis June 27, 2024, 10 a.m. UTC

From: Jerry Zhang Jian <jerry.zhangjian@sifive.com>

According to RISC-V crypto spec, Zvkb extension is a
subset of the Zvbb extension [1].

1: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com>
[ Changes by AF:
 - Tidy up commit message
 - Rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff mbox series

Patch

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 683f604d9f..fa8a17cc60 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -667,6 +667,10 @@  void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
+    if (cpu->cfg.ext_zvbb) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
+    }
+
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
          cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {