| Message ID | 20240626-smcntrpmf_v7-v7-4-bb0f10af7fa9@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V ISA extension smcntrpmf support | expand |
On Thu, Jun 27, 2024 at 9:58 AM Atish Patra <atishp@rivosinc.com> wrote: > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > This adds the definitions for ISA extension smcntrpmf. > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 6 ++++++ > target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++ > 2 files changed, 35 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 46faefd24e09..c5d289e5f4b9 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -339,6 +339,12 @@ struct CPUArchState { > > uint32_t mcountinhibit; > > + /* PMU cycle & instret privilege mode filtering */ > + target_ulong mcyclecfg; > + target_ulong mcyclecfgh; > + target_ulong minstretcfg; > + target_ulong minstretcfgh; > + > /* PMU counter state */ > PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index c257c5ed7dc9..5faa817453bb 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -397,6 +397,10 @@ > /* Machine counter-inhibit register */ > #define CSR_MCOUNTINHIBIT 0x320 > > +/* Machine counter configuration registers */ > +#define CSR_MCYCLECFG 0x321 > +#define CSR_MINSTRETCFG 0x322 > + > #define CSR_MHPMEVENT3 0x323 > #define CSR_MHPMEVENT4 0x324 > #define CSR_MHPMEVENT5 0x325 > @@ -427,6 +431,9 @@ > #define CSR_MHPMEVENT30 0x33e > #define CSR_MHPMEVENT31 0x33f > > +#define CSR_MCYCLECFGH 0x721 > +#define CSR_MINSTRETCFGH 0x722 > + > #define CSR_MHPMEVENT3H 0x723 > #define CSR_MHPMEVENT4H 0x724 > #define CSR_MHPMEVENT5H 0x725 > @@ -884,6 +891,28 @@ typedef enum RISCVException { > /* PMU related bits */ > #define MIE_LCOFIE (1 << IRQ_PMU_OVF) > > +#define MCYCLECFG_BIT_MINH BIT_ULL(62) > +#define MCYCLECFGH_BIT_MINH BIT(30) > +#define MCYCLECFG_BIT_SINH BIT_ULL(61) > +#define MCYCLECFGH_BIT_SINH BIT(29) > +#define MCYCLECFG_BIT_UINH BIT_ULL(60) > +#define MCYCLECFGH_BIT_UINH BIT(28) > +#define MCYCLECFG_BIT_VSINH BIT_ULL(59) > +#define MCYCLECFGH_BIT_VSINH BIT(27) > +#define MCYCLECFG_BIT_VUINH BIT_ULL(58) > +#define MCYCLECFGH_BIT_VUINH BIT(26) > + > +#define MINSTRETCFG_BIT_MINH BIT_ULL(62) > +#define MINSTRETCFGH_BIT_MINH BIT(30) > +#define MINSTRETCFG_BIT_SINH BIT_ULL(61) > +#define MINSTRETCFGH_BIT_SINH BIT(29) > +#define MINSTRETCFG_BIT_UINH BIT_ULL(60) > +#define MINSTRETCFGH_BIT_UINH BIT(28) > +#define MINSTRETCFG_BIT_VSINH BIT_ULL(59) > +#define MINSTRETCFGH_BIT_VSINH BIT(27) > +#define MINSTRETCFG_BIT_VUINH BIT_ULL(58) > +#define MINSTRETCFGH_BIT_VUINH BIT(26) > + > #define MHPMEVENT_BIT_OF BIT_ULL(63) > #define MHPMEVENTH_BIT_OF BIT(31) > #define MHPMEVENT_BIT_MINH BIT_ULL(62) > > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 46faefd24e09..c5d289e5f4b9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -339,6 +339,12 @@ struct CPUArchState { uint32_t mcountinhibit; + /* PMU cycle & instret privilege mode filtering */ + target_ulong mcyclecfg; + target_ulong mcyclecfgh; + target_ulong minstretcfg; + target_ulong minstretcfgh; + /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c257c5ed7dc9..5faa817453bb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -397,6 +397,10 @@ /* Machine counter-inhibit register */ #define CSR_MCOUNTINHIBIT 0x320 +/* Machine counter configuration registers */ +#define CSR_MCYCLECFG 0x321 +#define CSR_MINSTRETCFG 0x322 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 @@ -427,6 +431,9 @@ #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +#define CSR_MCYCLECFGH 0x721 +#define CSR_MINSTRETCFGH 0x722 + #define CSR_MHPMEVENT3H 0x723 #define CSR_MHPMEVENT4H 0x724 #define CSR_MHPMEVENT5H 0x725 @@ -884,6 +891,28 @@ typedef enum RISCVException { /* PMU related bits */ #define MIE_LCOFIE (1 << IRQ_PMU_OVF) +#define MCYCLECFG_BIT_MINH BIT_ULL(62) +#define MCYCLECFGH_BIT_MINH BIT(30) +#define MCYCLECFG_BIT_SINH BIT_ULL(61) +#define MCYCLECFGH_BIT_SINH BIT(29) +#define MCYCLECFG_BIT_UINH BIT_ULL(60) +#define MCYCLECFGH_BIT_UINH BIT(28) +#define MCYCLECFG_BIT_VSINH BIT_ULL(59) +#define MCYCLECFGH_BIT_VSINH BIT(27) +#define MCYCLECFG_BIT_VUINH BIT_ULL(58) +#define MCYCLECFGH_BIT_VUINH BIT(26) + +#define MINSTRETCFG_BIT_MINH BIT_ULL(62) +#define MINSTRETCFGH_BIT_MINH BIT(30) +#define MINSTRETCFG_BIT_SINH BIT_ULL(61) +#define MINSTRETCFGH_BIT_SINH BIT(29) +#define MINSTRETCFG_BIT_UINH BIT_ULL(60) +#define MINSTRETCFGH_BIT_UINH BIT(28) +#define MINSTRETCFG_BIT_VSINH BIT_ULL(59) +#define MINSTRETCFGH_BIT_VSINH BIT(27) +#define MINSTRETCFG_BIT_VUINH BIT_ULL(58) +#define MINSTRETCFGH_BIT_VUINH BIT(26) + #define MHPMEVENT_BIT_OF BIT_ULL(63) #define MHPMEVENTH_BIT_OF BIT(31) #define MHPMEVENT_BIT_MINH BIT_ULL(62)