diff mbox series

[PULL,04/61] target/riscv/cpu_cfg.h: remove unused fields

Message ID	20240209105813.3590056-5-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com>, Vladimir Isaev <vladimir.isaev@syntacore.com> Subject: [PULL 04/61] target/riscv/cpu_cfg.h: remove unused fields Date: Fri, 9 Feb 2024 20:57:16 +1000 Message-ID: <20240209105813.3590056-5-alistair.francis@wdc.com> In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions \| expand [PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions [PULL,02/61] target/riscv: Add infrastructure for 'B' MISA extension [PULL,03/61] target/riscv: Add step to validate 'B' extension [PULL,04/61] target/riscv/cpu_cfg.h: remove unused fields [PULL,05/61] target/riscv: make riscv_cpu_is_vendor() public [PULL,06/61] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] [PULL,07/61] target/riscv: move 'mmu' to riscv_cpu_properties[] [PULL,08/61] target/riscv: move 'pmp' to riscv_cpu_properties[] [PULL,09/61] target/riscv: rework 'priv_spec' [PULL,10/61] target/riscv: rework 'vext_spec' [PULL,11/61] target/riscv: move 'vlen' to riscv_cpu_properties[] [PULL,12/61] target/riscv: move 'elen' to riscv_cpu_properties[] [PULL,13/61] target/riscv: create finalize_features() for KVM [PULL,14/61] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] [PULL,15/61] target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[] [PULL,16/61] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[] [PULL,17/61] target/riscv: remove riscv_cpu_options[] [PULL,18/61] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] [PULL,19/61] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] [PULL,20/61] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] [PULL,21/61] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension [PULL,22/61] target/riscv: add 'vlenb' field in cpu->cfg [PULL,23/61] target/riscv/csr.c: use 'vlenb' instead of 'vlen' [PULL,24/61] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' [PULL,25/61] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb [PULL,26/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' [PULL,27/61] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb' [PULL,28/61] target/riscv/vector_helper.c: use 'vlenb' [PULL,29/61] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) [PULL,30/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() [PULL,31/61] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() [PULL,32/61] target/riscv: change vext_get_vlmax() arguments [PULL,33/61] trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v() [PULL,34/61] target/riscv/cpu.c: remove cpu->cfg.vlen [PULL,35/61] target/riscv/kvm: change kvm_reg_id to uint64_t [PULL,36/61] target/riscv/kvm: initialize 'vlenb' via get-reg-list [PULL,37/61] target/riscv/kvm: get/set vector vregs[] [PULL,38/61] target/riscv: Remove misa_mxl validation [PULL,39/61] target/riscv: Move misa_mxl_max to class [PULL,40/61] target/riscv: Validate misa_mxl_max only once [PULL,41/61] target/riscv: FCSR doesn't contain vxrm and vxsat [PULL,42/61] target/riscv: Use RISCVException as return type for all csr ops [PULL,43/61] hw/riscv/virt-acpi-build.c: fix leak in build_rhct() [PULL,44/61] hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix() [PULL,45/61] hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus() [PULL,46/61] hw/riscv/virt.c: use g_autofree in create_fdt_sockets() [PULL,47/61] hw/riscv/virt.c: use g_autofree in create_fdt_virtio() [PULL,48/61] hw/riscv/virt.c: use g_autofree in virt_machine_init() [PULL,49/61] hw/riscv/virt.c: use g_autofree in create_fdt_ [PULL,50/61] target/riscv: Add Zaamo and Zalrsc extension infrastructure [PULL,51/61] target/riscv: Check 'A' and split extensions for atomic instructions [PULL,52/61] target/riscv: Expose Zaamo and Zalrsc extensions [PULL,53/61] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS [PULL,54/61] target/riscv: support new isa extension detection devicetree properties [PULL,55/61] smbios: add processor-family option [PULL,56/61] smbios: function to set default processor family [PULL,57/61] target/riscv: SMBIOS support for RISC-V virt machine [PULL,58/61] qemu-options: enable -smbios option on RISC-V [PULL,59/61] target/riscv: Enable xtheadsync under user mode [PULL,60/61] target/riscv/cpu.c: add riscv_bare_cpu_init() [PULL,61/61] target/riscv: add rv32i, rv32e and rv64e CPUs

Commit Message

Alistair Francis Feb. 9, 2024, 10:57 a.m. UTC

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

user_spec, bext_spec and bext_ver aren't being used.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h     | 1 -
 target/riscv/cpu_cfg.h | 2 --
 2 files changed, 3 deletions(-)

diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 136fc1de73..52648e3af0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -181,7 +181,6 @@  struct CPUArchState {
     target_ulong guest_phys_fault_addr;
 
     target_ulong priv_ver;
-    target_ulong bext_ver;
     target_ulong vext_ver;
 
     /* RISCVMXL, but uint32_t for vmstate migration */
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 780ae6ef17..0612668144 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -140,8 +140,6 @@  struct RISCVCPUConfig {
 
     uint32_t pmu_mask;
     char *priv_spec;
-    char *user_spec;
-    char *bext_spec;
     char *vext_spec;
     uint16_t vlen;
     uint16_t elen;