[PULL,42/61] target/riscv: Use RISCVException as return type for all csr ops

Message ID	20240209105813.3590056-43-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, Alistair Francis <alistair.francis@wdc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 42/61] target/riscv: Use RISCVException as return type for all csr ops Date: Fri, 9 Feb 2024 20:57:54 +1000 Message-ID: <20240209105813.3590056-43-alistair.francis@wdc.com> In-Reply-To: <20240209105813.3590056-1-alistair.francis@wdc.com> References: <20240209105813.3590056-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::12b; envelope-from=alistair23@gmail.com; helo=mail-il1-x12b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions \| expand [PULL,01/61] target/riscv: Check for 'A' extension on all atomic instructions [PULL,02/61] target/riscv: Add infrastructure for 'B' MISA extension [PULL,03/61] target/riscv: Add step to validate 'B' extension [PULL,04/61] target/riscv/cpu_cfg.h: remove unused fields [PULL,05/61] target/riscv: make riscv_cpu_is_vendor() public [PULL,06/61] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] [PULL,07/61] target/riscv: move 'mmu' to riscv_cpu_properties[] [PULL,08/61] target/riscv: move 'pmp' to riscv_cpu_properties[] [PULL,09/61] target/riscv: rework 'priv_spec' [PULL,10/61] target/riscv: rework 'vext_spec' [PULL,11/61] target/riscv: move 'vlen' to riscv_cpu_properties[] [PULL,12/61] target/riscv: move 'elen' to riscv_cpu_properties[] [PULL,13/61] target/riscv: create finalize_features() for KVM [PULL,14/61] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] [PULL,15/61] target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[] [PULL,16/61] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[] [PULL,17/61] target/riscv: remove riscv_cpu_options[] [PULL,18/61] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] [PULL,19/61] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] [PULL,20/61] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] [PULL,21/61] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension [PULL,22/61] target/riscv: add 'vlenb' field in cpu->cfg [PULL,23/61] target/riscv/csr.c: use 'vlenb' instead of 'vlen' [PULL,24/61] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' [PULL,25/61] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb [PULL,26/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' [PULL,27/61] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb' [PULL,28/61] target/riscv/vector_helper.c: use 'vlenb' [PULL,29/61] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) [PULL,30/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() [PULL,31/61] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() [PULL,32/61] target/riscv: change vext_get_vlmax() arguments [PULL,33/61] trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v() [PULL,34/61] target/riscv/cpu.c: remove cpu->cfg.vlen [PULL,35/61] target/riscv/kvm: change kvm_reg_id to uint64_t [PULL,36/61] target/riscv/kvm: initialize 'vlenb' via get-reg-list [PULL,37/61] target/riscv/kvm: get/set vector vregs[] [PULL,38/61] target/riscv: Remove misa_mxl validation [PULL,39/61] target/riscv: Move misa_mxl_max to class [PULL,40/61] target/riscv: Validate misa_mxl_max only once [PULL,41/61] target/riscv: FCSR doesn't contain vxrm and vxsat [PULL,42/61] target/riscv: Use RISCVException as return type for all csr ops [PULL,43/61] hw/riscv/virt-acpi-build.c: fix leak in build_rhct() [PULL,44/61] hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix() [PULL,45/61] hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus() [PULL,46/61] hw/riscv/virt.c: use g_autofree in create_fdt_sockets() [PULL,47/61] hw/riscv/virt.c: use g_autofree in create_fdt_virtio() [PULL,48/61] hw/riscv/virt.c: use g_autofree in virt_machine_init() [PULL,49/61] hw/riscv/virt.c: use g_autofree in create_fdt_ [PULL,50/61] target/riscv: Add Zaamo and Zalrsc extension infrastructure [PULL,51/61] target/riscv: Check 'A' and split extensions for atomic instructions [PULL,52/61] target/riscv: Expose Zaamo and Zalrsc extensions [PULL,53/61] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS [PULL,54/61] target/riscv: support new isa extension detection devicetree properties [PULL,55/61] smbios: add processor-family option [PULL,56/61] smbios: function to set default processor family [PULL,57/61] target/riscv: SMBIOS support for RISC-V virt machine [PULL,58/61] qemu-options: enable -smbios option on RISC-V [PULL,59/61] target/riscv: Enable xtheadsync under user mode [PULL,60/61] target/riscv/cpu.c: add riscv_bare_cpu_init() [PULL,61/61] target/riscv: add rv32i, rv32e and rv64e CPUs

diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d9a010387f..d4e8ac13b9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -242,7 +242,7 @@ static RISCVException any32(CPURISCVState *env, int csrno) } -static int aia_any(CPURISCVState *env, int csrno) +static RISCVException aia_any(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -251,7 +251,7 @@ static int aia_any(CPURISCVState *env, int csrno) return any(env, csrno); } -static int aia_any32(CPURISCVState *env, int csrno) +static RISCVException aia_any32(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -269,7 +269,7 @@ static RISCVException smode(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } -static int smode32(CPURISCVState *env, int csrno) +static RISCVException smode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) != MXL_RV32) { return RISCV_EXCP_ILLEGAL_INST; @@ -278,7 +278,7 @@ static int smode32(CPURISCVState *env, int csrno) return smode(env, csrno); } -static int aia_smode(CPURISCVState *env, int csrno) +static RISCVException aia_smode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -287,7 +287,7 @@ static int aia_smode(CPURISCVState *env, int csrno) return smode(env, csrno); } -static int aia_smode32(CPURISCVState *env, int csrno) +static RISCVException aia_smode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -496,7 +496,7 @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } -static int aia_hmode(CPURISCVState *env, int csrno) +static RISCVException aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -505,7 +505,7 @@ static int aia_hmode(CPURISCVState *env, int csrno) return hmode(env, csrno); } -static int aia_hmode32(CPURISCVState *env, int csrno) +static RISCVException aia_hmode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -681,7 +681,8 @@ static RISCVException read_vl(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vlenb(CPURISCVState *env, int csrno, + target_ulong *val) { *val = riscv_cpu_cfg(env)->vlenb; return RISCV_EXCP_NONE; @@ -742,13 +743,15 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vcsr(CPURISCVState *env, int csrno, + target_ulong *val) { *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); return RISCV_EXCP_NONE; } -static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_vcsr(CPURISCVState *env, int csrno, + target_ulong val) { #if !defined(CONFIG_USER_ONLY) env->mstatus |= MSTATUS_VS; @@ -798,13 +801,15 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, + target_ulong *val) { *val = get_ticks(false); return RISCV_EXCP_NONE; } -static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, + target_ulong *val) { *val = get_ticks(true); return RISCV_EXCP_NONE; @@ -812,7 +817,8 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) #else /* CONFIG_USER_ONLY */ -static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, + target_ulong *val) { int evt_index = csrno - CSR_MCOUNTINHIBIT; @@ -821,7 +827,8 @@ static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) return RISCV_EXCP_NONE; } -static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mhpmevent(CPURISCVState *env, int csrno, + target_ulong val) { int evt_index = csrno - CSR_MCOUNTINHIBIT; uint64_t mhpmevt_val = val; @@ -837,7 +844,8 @@ static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val) return RISCV_EXCP_NONE; } -static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno, + target_ulong *val) { int evt_index = csrno - CSR_MHPMEVENT3H + 3; @@ -846,7 +854,8 @@ static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val) return RISCV_EXCP_NONE; } -static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno, + target_ulong val) { int evt_index = csrno - CSR_MHPMEVENT3H + 3; uint64_t mhpmevth_val = val; @@ -860,7 +869,8 @@ static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val) return RISCV_EXCP_NONE; } -static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, + target_ulong val) { int ctr_idx = csrno - CSR_MCYCLE; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; @@ -885,7 +895,8 @@ static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val) return RISCV_EXCP_NONE; } -static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, + target_ulong val) { int ctr_idx = csrno - CSR_MCYCLEH; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; @@ -945,7 +956,8 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, return RISCV_EXCP_NONE; } -static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, + target_ulong *val) { uint16_t ctr_index; @@ -960,7 +972,8 @@ static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) return riscv_pmu_read_ctr(env, val, false, ctr_index); } -static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, + target_ulong *val) { uint16_t ctr_index; @@ -975,7 +988,8 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) return riscv_pmu_read_ctr(env, val, true, ctr_index); } -static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_scountovf(CPURISCVState *env, int csrno, + target_ulong *val) { int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; int i; @@ -1638,7 +1652,8 @@ static RISCVException rmw_mvienh(CPURISCVState *env, int csrno, return ret; } -static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_mtopi(CPURISCVState *env, int csrno, + target_ulong *val) { int irq; uint8_t iprio; @@ -1678,8 +1693,9 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) }; } -static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) +static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) { target_ulong *iselect; @@ -1758,8 +1774,9 @@ static int rmw_iprio(target_ulong xlen, return 0; } -static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) +static RISCVException rmw_xireg(CPURISCVState *env, int csrno, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) { bool virt, isel_reserved; uint8_t *iprio; @@ -1833,8 +1850,9 @@ done: return RISCV_EXCP_NONE; } -static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) +static RISCVException rmw_xtopei(CPURISCVState *env, int csrno, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) { bool virt; int ret = -EINVAL; @@ -3031,7 +3049,8 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vstopi(CPURISCVState *env, int csrno, + target_ulong *val) { int irq, ret; target_ulong topei; @@ -3120,7 +3139,8 @@ static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) return RISCV_EXCP_NONE; } -static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_stopi(CPURISCVState *env, int csrno, + target_ulong *val) { int irq; uint8_t iprio; @@ -3576,19 +3596,21 @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hvictl(CPURISCVState *env, int csrno, + target_ulong *val) { *val = env->hvictl; return RISCV_EXCP_NONE; } -static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hvictl(CPURISCVState *env, int csrno, + target_ulong val) { env->hvictl = val & HVICTL_VALID_MASK; return RISCV_EXCP_NONE; } -static int read_hvipriox(CPURISCVState *env, int first_index, +static RISCVException read_hvipriox(CPURISCVState *env, int first_index, uint8_t *iprio, target_ulong *val) { int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); @@ -3614,7 +3636,7 @@ static int read_hvipriox(CPURISCVState *env, int first_index, return RISCV_EXCP_NONE; } -static int write_hvipriox(CPURISCVState *env, int first_index, +static RISCVException write_hvipriox(CPURISCVState *env, int first_index, uint8_t *iprio, target_ulong val) { int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); @@ -3640,42 +3662,50 @@ static int write_hvipriox(CPURISCVState *env, int first_index, return RISCV_EXCP_NONE; } -static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hviprio1(CPURISCVState *env, int csrno, + target_ulong *val) { return read_hvipriox(env, 0, env->hviprio, val); } -static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hviprio1(CPURISCVState *env, int csrno, + target_ulong val) { return write_hvipriox(env, 0, env->hviprio, val); } -static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hviprio1h(CPURISCVState *env, int csrno, + target_ulong *val) { return read_hvipriox(env, 4, env->hviprio, val); } -static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hviprio1h(CPURISCVState *env, int csrno, + target_ulong val) { return write_hvipriox(env, 4, env->hviprio, val); } -static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hviprio2(CPURISCVState *env, int csrno, + target_ulong *val) { return read_hvipriox(env, 8, env->hviprio, val); } -static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hviprio2(CPURISCVState *env, int csrno, + target_ulong val) { return write_hvipriox(env, 8, env->hviprio, val); } -static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_hviprio2h(CPURISCVState *env, int csrno, + target_ulong *val) { return read_hvipriox(env, 12, env->hviprio, val); } -static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) +static RISCVException write_hviprio2h(CPURISCVState *env, int csrno, + target_ulong val) { return write_hvipriox(env, 12, env->hviprio, val); } @@ -3699,7 +3729,8 @@ static RISCVException write_vsstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) +static RISCVException read_vstvec(CPURISCVState *env, int csrno, + target_ulong *val) { *val = env->vstvec; return RISCV_EXCP_NONE;

[PULL,42/61] target/riscv: Use RISCVException as return type for all csr ops

Commit Message

Patch