| Message ID | 20240202152154.773253-5-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: named features riscv,isa, 'svade' rework | expand |
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > From: Andrew Jones <ajones@ventanamicro.com> > > The hypervisor should decide what it wants to enable. Zero all > configuration enable bits on reset. > > Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for > svadu extension") missed one reference to 'hade'. Change it now. > > Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation") > Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension") > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 3 +-- > target/riscv/csr.c | 2 +- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 94843c4f6e..9045f87481 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj) > > env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | > (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); > - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | > - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); > + env->henvcfg = 0; > > /* Initialized default priorities of local interrupts. */ > for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d9a010387f..93f7bc2cb4 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2115,7 +2115,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > /* > * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 > * henvcfg.stce is read_only 0 when menvcfg.stce = 0 > - * henvcfg.hade is read_only 0 when menvcfg.hade = 0 > + * henvcfg.adue is read_only 0 when menvcfg.adue = 0 > */ > *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | > env->menvcfg); > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 94843c4f6e..9045f87481 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj) env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); + env->henvcfg = 0; /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d9a010387f..93f7bc2cb4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2115,7 +2115,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, /* * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 - * henvcfg.hade is read_only 0 when menvcfg.hade = 0 + * henvcfg.adue is read_only 0 when menvcfg.adue = 0 */ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | env->menvcfg);