| Message ID | 20240109102930.405323-5-me@deliversmonkey.space |
|---|---|
| State | New |
| Headers | show |
| Series | Pointer Masking update for Zjpm v0.8 | expand |
On Tue, Jan 9, 2024 at 8:31 PM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > From: Alexey Baturo <baturo.alexey@gmail.com> > > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 3 +++ > target/riscv/cpu_helper.c | 3 +++ > target/riscv/translate.c | 5 +++++ > 3 files changed, 11 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 1c8979c1c8..0284ea418f 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -545,6 +545,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1) > FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) > FIELD(TB_FLAGS, PRIV, 22, 2) > FIELD(TB_FLAGS, AXL, 24, 2) > +/* If pointer masking should be applied and address sign extended */ > +FIELD(TB_FLAGS, PM_PMM, 26, 2) > +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1) > > #ifdef TARGET_RISCV32 > #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9640e4c2c5..67bc51e510 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, > RISCVCPU *cpu = env_archcpu(env); > RISCVExtStatus fs, vs; > uint32_t flags = 0; > + bool pm_signext = riscv_cpu_virt_mem_enabled(env); > > *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; > *cs_base = 0; > @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, > flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); > flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); > flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); > + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); > + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); > > *pflags = flags; > } > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 6b4b9a671c..2c89d749c0 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -103,6 +103,9 @@ typedef struct DisasContext { > bool vl_eq_vlmax; > CPUState *cs; > TCGv zero; > + /* actual address width */ > + uint8_t addr_width; > + bool addr_signed; > /* Use icount trigger for native debug */ > bool itrigger; > /* FRM is known to contain a valid value. */ > @@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); > ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); > ctx->cs = cs; > + ctx->addr_width = 0; > + ctx->addr_signed = false; > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > ctx->zero = tcg_constant_tl(0); > ctx->virt_inst_excp = false; > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1c8979c1c8..0284ea418f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -545,6 +545,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) FIELD(TB_FLAGS, PRIV, 22, 2) FIELD(TB_FLAGS, AXL, 24, 2) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 26, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9640e4c2c5..67bc51e510 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu = env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags = 0; + bool pm_signext = riscv_cpu_virt_mem_enabled(env); *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6b4b9a671c..2c89d749c0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -103,6 +103,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* actual address width */ + uint8_t addr_width; + bool addr_signed; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; + ctx->addr_width = 0; + ctx->addr_signed = false; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false;