| Message ID | 20240108161903.353648-2-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: add rv32i,rv32e and rv64e CPUs | expand |
On Tue, Jan 9, 2024 at 3:32 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Next patch will add more bare CPUs. Their cpu_init() functions would be > glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a > riscv_cpu_set_misa() call. > > Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this > code repetition. While we're at it, add a better explanation on why > we're disabling the timing extensions for bare CPUs. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++---------------- > 1 file changed, 29 insertions(+), 16 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b32681f7f3..1202ec3e57 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -575,22 +575,6 @@ static void rv64i_bare_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > riscv_cpu_set_misa(env, MXL_RV64, RVI); > - > - /* Remove the defaults from the parent class */ > - RISCV_CPU(obj)->cfg.ext_zicntr = false; > - RISCV_CPU(obj)->cfg.ext_zihpm = false; > - > - /* Set to QEMU's first supported priv version */ > - env->priv_ver = PRIV_VERSION_1_10_0; > - > - /* > - * Support all available satp_mode settings. The default > - * value will be set to MBARE if the user doesn't set > - * satp_mode manually (see set_satp_mode_default()). > - */ > -#ifndef CONFIG_USER_ONLY > - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); > -#endif > } > #else > static void rv32_base_cpu_init(Object *obj) > @@ -1266,6 +1250,34 @@ static void riscv_cpu_init(Object *obj) > RISCV_CPU(obj)->cfg.ext_zihpm = true; > } > > +static void riscv_bare_cpu_init(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + /* > + * Bare CPUs do not inherit the timer and performance > + * counters from the parent class (see riscv_cpu_init() > + * for info on why the parent enables them). > + * > + * Users have to explicitly enable these counters for > + * bare CPUs. > + */ > + cpu->cfg.ext_zicntr = false; > + cpu->cfg.ext_zihpm = false; > + > + /* Set to QEMU's first supported priv version */ > + cpu->env.priv_ver = PRIV_VERSION_1_10_0; > + > + /* > + * Support all available satp_mode settings. The default > + * value will be set to MBARE if the user doesn't set > + * satp_mode manually (see set_satp_mode_default()). > + */ > +#ifndef CONFIG_USER_ONLY > + set_satp_mode_max_supported(cpu, VM_1_10_SV64); > +#endif > +} > + > typedef struct misa_ext_info { > const char *name; > const char *description; > @@ -1925,6 +1937,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > { > .name = TYPE_RISCV_BARE_CPU, > .parent = TYPE_RISCV_CPU, > + .instance_init = riscv_bare_cpu_init, > .abstract = true, > }, > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b32681f7f3..1202ec3e57 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,22 +575,6 @@ static void rv64i_bare_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; riscv_cpu_set_misa(env, MXL_RV64, RVI); - - /* Remove the defaults from the parent class */ - RISCV_CPU(obj)->cfg.ext_zicntr = false; - RISCV_CPU(obj)->cfg.ext_zihpm = false; - - /* Set to QEMU's first supported priv version */ - env->priv_ver = PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); -#endif } #else static void rv32_base_cpu_init(Object *obj) @@ -1266,6 +1250,34 @@ static void riscv_cpu_init(Object *obj) RISCV_CPU(obj)->cfg.ext_zihpm = true; } +static void riscv_bare_cpu_init(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + cpu->cfg.ext_zicntr = false; + cpu->cfg.ext_zihpm = false; + + /* Set to QEMU's first supported priv version */ + cpu->env.priv_ver = PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV64); +#endif +} + typedef struct misa_ext_info { const char *name; const char *description; @@ -1925,6 +1937,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_RISCV_BARE_CPU, .parent = TYPE_RISCV_CPU, + .instance_init = riscv_bare_cpu_init, .abstract = true, }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
Next patch will add more bare CPUs. Their cpu_init() functions would be glorified copy/pastes of rv64i_bare_cpu_init(), differing only by a riscv_cpu_set_misa() call. Add a new .instance_init for the TYPE_RISCV_BARE_CPU typ to avoid this code repetition. While we're at it, add a better explanation on why we're disabling the timing extensions for bare CPUs. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 16 deletions(-)