diff mbox series

[v4,16/17] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]

Message ID 20240105230546.265053-17-dbarboza@ventanamicro.com
State New
Headers show
Series target/riscv: deprecate riscv_cpu_options[] | expand

Commit Message

Daniel Henrique Barboza Jan. 5, 2024, 11:05 p.m. UTC 
Keep all class properties in riscv_cpu_properties[].

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 68 ++++++++++++++++++++++++----------------------
 1 file changed, 36 insertions(+), 32 deletions(-)

Comments

Alistair Francis Jan. 12, 2024, 1:29 a.m. UTC | #1 
On Sat, Jan 6, 2024 at 9:07 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Keep all class properties in riscv_cpu_properties[].
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 68 ++++++++++++++++++++++++----------------------
>  1 file changed, 36 insertions(+), 32 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c725a4839d..6149f5960e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2009,6 +2009,41 @@ static const PropertyInfo prop_mvendorid = {
>      .set = prop_mvendorid_set,
>  };
>
> +static void prop_mimpid_set(Object *obj, Visitor *v, const char *name,
> +                            void *opaque, Error **errp)
> +{
> +    bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
> +    RISCVCPU *cpu = RISCV_CPU(obj);
> +    uint64_t prev_val = cpu->cfg.mimpid;
> +    uint64_t value;
> +
> +    if (!visit_type_uint64(v, name, &value, errp)) {
> +        return;
> +    }
> +
> +    if (!dynamic_cpu && prev_val != value) {
> +        error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
> +                   object_get_typename(obj), prev_val);
> +        return;
> +    }
> +
> +    cpu->cfg.mimpid = value;
> +}
> +
> +static void prop_mimpid_get(Object *obj, Visitor *v, const char *name,
> +                            void *opaque, Error **errp)
> +{
> +    uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
> +
> +    visit_type_uint64(v, name, &value, errp);
> +}
> +
> +static const PropertyInfo prop_mimpid = {
> +    .name = "mimpid",
> +    .get = prop_mimpid_get,
> +    .set = prop_mimpid_set,
> +};
> +
>  /*
>   * RVA22U64 defines some 'named features' or 'synthetic extensions'
>   * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
> @@ -2096,6 +2131,7 @@ static Property riscv_cpu_properties[] = {
>      {.name = "cboz_blocksize", .info = &prop_cboz_blksize},
>
>       {.name = "mvendorid", .info = &prop_mvendorid},
> +     {.name = "mimpid", .info = &prop_mimpid},
>
>  #ifndef CONFIG_USER_ONLY
>      DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
> @@ -2177,35 +2213,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
>  };
>  #endif
>
> -static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
> -                           void *opaque, Error **errp)
> -{
> -    bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
> -    RISCVCPU *cpu = RISCV_CPU(obj);
> -    uint64_t prev_val = cpu->cfg.mimpid;
> -    uint64_t value;
> -
> -    if (!visit_type_uint64(v, name, &value, errp)) {
> -        return;
> -    }
> -
> -    if (!dynamic_cpu && prev_val != value) {
> -        error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
> -                   object_get_typename(obj), prev_val);
> -        return;
> -    }
> -
> -    cpu->cfg.mimpid = value;
> -}
> -
> -static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
> -                           void *opaque, Error **errp)
> -{
> -    uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
> -
> -    visit_type_uint64(v, name, &value, errp);
> -}
> -
>  static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
>                              void *opaque, Error **errp)
>  {
> @@ -2286,9 +2293,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
>      cc->gdb_arch_name = riscv_gdb_arch_name;
>      cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
>
> -    object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
> -                              cpu_set_mimpid, NULL, NULL);
> -
>      object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
>                                cpu_set_marchid, NULL, NULL);
>
> --
> 2.43.0
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c725a4839d..6149f5960e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2009,6 +2009,41 @@  static const PropertyInfo prop_mvendorid = {
     .set = prop_mvendorid_set,
 };
 
+static void prop_mimpid_set(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    uint64_t prev_val = cpu->cfg.mimpid;
+    uint64_t value;
+
+    if (!visit_type_uint64(v, name, &value, errp)) {
+        return;
+    }
+
+    if (!dynamic_cpu && prev_val != value) {
+        error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
+                   object_get_typename(obj), prev_val);
+        return;
+    }
+
+    cpu->cfg.mimpid = value;
+}
+
+static void prop_mimpid_get(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
+
+    visit_type_uint64(v, name, &value, errp);
+}
+
+static const PropertyInfo prop_mimpid = {
+    .name = "mimpid",
+    .get = prop_mimpid_get,
+    .set = prop_mimpid_set,
+};
+
 /*
  * RVA22U64 defines some 'named features' or 'synthetic extensions'
  * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
@@ -2096,6 +2131,7 @@  static Property riscv_cpu_properties[] = {
     {.name = "cboz_blocksize", .info = &prop_cboz_blksize},
 
      {.name = "mvendorid", .info = &prop_mvendorid},
+     {.name = "mimpid", .info = &prop_mimpid},
 
 #ifndef CONFIG_USER_ONLY
     DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
@@ -2177,35 +2213,6 @@  static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
-                           void *opaque, Error **errp)
-{
-    bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
-    RISCVCPU *cpu = RISCV_CPU(obj);
-    uint64_t prev_val = cpu->cfg.mimpid;
-    uint64_t value;
-
-    if (!visit_type_uint64(v, name, &value, errp)) {
-        return;
-    }
-
-    if (!dynamic_cpu && prev_val != value) {
-        error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
-                   object_get_typename(obj), prev_val);
-        return;
-    }
-
-    cpu->cfg.mimpid = value;
-}
-
-static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
-                           void *opaque, Error **errp)
-{
-    uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
-
-    visit_type_uint64(v, name, &value, errp);
-}
-
 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
                             void *opaque, Error **errp)
 {
@@ -2286,9 +2293,6 @@  static void riscv_cpu_class_init(ObjectClass *c, void *data)
     cc->gdb_arch_name = riscv_gdb_arch_name;
     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 
-    object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
-                              cpu_set_mimpid, NULL, NULL);
-
     object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
                               cpu_set_marchid, NULL, NULL);