| Message ID | 20231218125334.37184-24-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: RVA22 profiles support | expand |
On Mon, Dec 18, 2023 at 10:56 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > 'satp_mode' is a requirement for supervisor profiles like RVA22S64. > User-mode/application profiles like RVA22U64 doesn't care. > > Add 'satp_mode' to the profile description. If a profile requires it, > set it during cpu_set_profile(). We'll also check it during finalize() > to validate if the running config implements the profile. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/tcg/tcg-cpu.c | 40 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 42 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1dea5db52d..6795f5da41 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1543,6 +1543,7 @@ static RISCVCPUProfile RVA22U64 = { > .name = "rva22u64", > .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, > .priv_spec = RISCV_PROFILE_ATTR_UNUSED, > + .satp_mode = RISCV_PROFILE_ATTR_UNUSED, > .ext_offsets = { > CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), > CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 485d2da3c2..6c5fceb5f5 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -82,6 +82,7 @@ typedef struct riscv_cpu_profile { > bool enabled; > bool user_set; > int priv_spec; > + int satp_mode; > const int32_t ext_offsets[]; > } RISCVCPUProfile; > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 4d25fc43d2..152f95718b 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -766,6 +766,31 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > riscv_cpu_disable_priv_spec_isa_exts(cpu); > } > > +#ifndef CONFIG_USER_ONLY > +static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, > + RISCVCPUProfile *profile, > + bool send_warn) > +{ > + int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > + > + if (profile->satp_mode > satp_max) { > + if (send_warn) { > + bool is_32bit = riscv_cpu_is_32bit(cpu); > + const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); > + const char *cur_satp = satp_mode_str(satp_max, is_32bit); > + > + warn_report("Profile %s requires satp mode %s, " > + "but satp mode %s was set", profile->name, > + req_satp, cur_satp); > + } > + > + return false; > + } > + > + return true; > +} > +#endif > + > static void riscv_cpu_validate_profile(RISCVCPU *cpu, > RISCVCPUProfile *profile) > { > @@ -775,6 +800,13 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, > bool profile_impl = true; > int i; > > +#ifndef CONFIG_USER_ONLY > + if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { > + profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, > + send_warn); > + } > +#endif > + > if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && > profile->priv_spec != env->priv_ver) { > profile_impl = false; > @@ -1079,6 +1111,14 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, > cpu->env.priv_ver = profile->priv_spec; > } > > +#ifndef CONFIG_USER_ONLY > + if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { > + const char *satp_prop = satp_mode_str(profile->satp_mode, > + riscv_cpu_is_32bit(cpu)); > + object_property_set_bool(obj, satp_prop, profile->enabled, NULL); > + } > +#endif > + > for (i = 0; misa_bits[i] != 0; i++) { > uint32_t bit = misa_bits[i]; > > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1dea5db52d..6795f5da41 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1543,6 +1543,7 @@ static RISCVCPUProfile RVA22U64 = { .name = "rva22u64", .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, .priv_spec = RISCV_PROFILE_ATTR_UNUSED, + .satp_mode = RISCV_PROFILE_ATTR_UNUSED, .ext_offsets = { CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 485d2da3c2..6c5fceb5f5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ typedef struct riscv_cpu_profile { bool enabled; bool user_set; int priv_spec; + int satp_mode; const int32_t ext_offsets[]; } RISCVCPUProfile; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4d25fc43d2..152f95718b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -766,6 +766,31 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } +#ifndef CONFIG_USER_ONLY +static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, + RISCVCPUProfile *profile, + bool send_warn) +{ + int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); + + if (profile->satp_mode > satp_max) { + if (send_warn) { + bool is_32bit = riscv_cpu_is_32bit(cpu); + const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); + const char *cur_satp = satp_mode_str(satp_max, is_32bit); + + warn_report("Profile %s requires satp mode %s, " + "but satp mode %s was set", profile->name, + req_satp, cur_satp); + } + + return false; + } + + return true; +} +#endif + static void riscv_cpu_validate_profile(RISCVCPU *cpu, RISCVCPUProfile *profile) { @@ -775,6 +800,13 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, bool profile_impl = true; int i; +#ifndef CONFIG_USER_ONLY + if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { + profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, + send_warn); + } +#endif + if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && profile->priv_spec != env->priv_ver) { profile_impl = false; @@ -1079,6 +1111,14 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, cpu->env.priv_ver = profile->priv_spec; } +#ifndef CONFIG_USER_ONLY + if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { + const char *satp_prop = satp_mode_str(profile->satp_mode, + riscv_cpu_is_32bit(cpu)); + object_property_set_bool(obj, satp_prop, profile->enabled, NULL); + } +#endif + for (i = 0; misa_bits[i] != 0; i++) { uint32_t bit = misa_bits[i];