| Message ID | 20231031154000.18134-5-rbradford@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Support discontinuous PMU counters | expand |
On Wed, Nov 1, 2023 at 1:41 AM Rob Bradford <rbradford@rivosinc.com> wrote: > > Using a mask instead of the number of PMU devices supports the accurate > emulation of platforms that have a discontinuous set of PMU counters. > > The "pmu-num" property now generates a warning when used by the user on > the command line. > > Rather than storing the value for "pmu-num" convert it directly to the > mask if it is specified (overwriting the default "pmu-mask" value) > likewise the value is calculated from the mask if the property value is > obtained. > > In the unusual situation that both "pmu-mask" and "pmu-num" are provided > then then the order on the command line determines which takes > precedence (later overwriting earlier.) > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 40 +++++++++++++++++++++++++++++++++++++- > target/riscv/cpu_cfg.h | 2 +- > target/riscv/machine.c | 2 +- > target/riscv/pmu.c | 15 +++++++------- > target/riscv/tcg/tcg-cpu.c | 2 +- > 5 files changed, 50 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ac4a6c7eec..51accdba5f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1362,8 +1362,46 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + uint8_t pmu_num; > + > + visit_type_uint8(v, name, &pmu_num, errp); > + > + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { > + error_setg(errp, "Number of counters exceeds maximum available"); > + return; > + } > + > + if (pmu_num == 0) { > + cpu->cfg.pmu_mask = 0; > + } else { > + cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); > + } > + > + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); > +} > + > +static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + uint8_t pmu_num = ctpop32(cpu->cfg.pmu_mask); > + > + visit_type_uint8(v, name, &pmu_num, errp); > +} > + > +const PropertyInfo prop_pmu_num = { > + .name = "pmu-num", > + .get = prop_pmu_num_get, > + .set = prop_pmu_num_set, > +}; > + > Property riscv_cpu_options[] = { > - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), > + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)), > + {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 0e6a0f245c..f4e6f273fc 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -123,7 +123,7 @@ struct RISCVCPUConfig { > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > > - uint8_t pmu_num; > + uint32_t pmu_mask; > char *priv_spec; > char *user_spec; > char *bext_spec; > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index c7c862cdd3..9f6e3f7a6d 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -313,7 +313,7 @@ static bool pmu_needed(void *opaque) > { > RISCVCPU *cpu = opaque; > > - return cpu->cfg.pmu_num; > + return (cpu->cfg.pmu_mask > 0); > } > > static const VMStateDescription vmstate_pmu_ctr_state = { > diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c > index 7ddf4977b1..0e7d58b8a5 100644 > --- a/target/riscv/pmu.c > +++ b/target/riscv/pmu.c > @@ -18,14 +18,13 @@ > > #include "qemu/osdep.h" > #include "qemu/log.h" > +#include "qemu/error-report.h" > #include "cpu.h" > #include "pmu.h" > #include "sysemu/cpu-timers.h" > #include "sysemu/device_tree.h" > > #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ > -#define MAKE_32BIT_MASK(shift, length) \ > - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) > > /* > * To keep it simple, any event can be mapped to any programmable counters in > @@ -184,7 +183,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) > CPURISCVState *env = &cpu->env; > gpointer value; > > - if (!cpu->cfg.pmu_num) { > + if (!cpu->cfg.pmu_mask) { > return 0; > } > value = g_hash_table_lookup(cpu->pmu_event_ctr_map, > @@ -432,9 +431,12 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) > > void riscv_pmu_init(RISCVCPU *cpu, Error **errp) > { > - uint8_t pmu_num = cpu->cfg.pmu_num; > + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { > + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); > + return; > + } > > - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { > + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3)) { > error_setg(errp, "Number of counters exceeds maximum available"); > return; > } > @@ -445,6 +447,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) > return; > } > > - /* Create a bitmask of available programmable counters */ > - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); > + cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; > } > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index ed3eb991c0..53c52389b9 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -613,7 +613,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) > riscv_timer_init(cpu); > } > > - if (cpu->cfg.pmu_num) { > + if (cpu->cfg.pmu_mask) { > riscv_pmu_init(cpu, &local_err); > if (local_err != NULL) { > error_propagate(errp, local_err); > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..51accdba5f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1362,8 +1362,46 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + uint8_t pmu_num; + + visit_type_uint8(v, name, &pmu_num, errp); + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; + } + + if (pmu_num == 0) { + cpu->cfg.pmu_mask = 0; + } else { + cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); + } + + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); +} + +static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + uint8_t pmu_num = ctpop32(cpu->cfg.pmu_mask); + + visit_type_uint8(v, name, &pmu_num, errp); +} + +const PropertyInfo prop_pmu_num = { + .name = "pmu-num", + .get = prop_pmu_num_get, + .set = prop_pmu_num_set, +}; + Property riscv_cpu_options[] = { - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)), + {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..f4e6f273fc 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -123,7 +123,7 @@ struct RISCVCPUConfig { bool ext_xtheadsync; bool ext_XVentanaCondOps; - uint8_t pmu_num; + uint32_t pmu_mask; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..9f6e3f7a6d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -313,7 +313,7 @@ static bool pmu_needed(void *opaque) { RISCVCPU *cpu = opaque; - return cpu->cfg.pmu_num; + return (cpu->cfg.pmu_mask > 0); } static const VMStateDescription vmstate_pmu_ctr_state = { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 7ddf4977b1..0e7d58b8a5 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -18,14 +18,13 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" #include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) /* * To keep it simple, any event can be mapped to any programmable counters in @@ -184,7 +183,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) CPURISCVState *env = &cpu->env; gpointer value; - if (!cpu->cfg.pmu_num) { + if (!cpu->cfg.pmu_mask) { return 0; } value = g_hash_table_lookup(cpu->pmu_event_ctr_map, @@ -432,9 +431,12 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - uint8_t pmu_num = cpu->cfg.pmu_num; + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); + return; + } - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } @@ -445,6 +447,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } - /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); + cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ed3eb991c0..53c52389b9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -613,7 +613,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) riscv_timer_init(cpu); } - if (cpu->cfg.pmu_num) { + if (cpu->cfg.pmu_mask) { riscv_pmu_init(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err);
Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters. The "pmu-num" property now generates a warning when used by the user on the command line. Rather than storing the value for "pmu-num" convert it directly to the mask if it is specified (overwriting the default "pmu-mask" value) likewise the value is calculated from the mask if the property value is obtained. In the unusual situation that both "pmu-mask" and "pmu-num" are provided then then the order on the command line determines which takes precedence (later overwriting earlier.) Signed-off-by: Rob Bradford <rbradford@rivosinc.com> --- target/riscv/cpu.c | 40 +++++++++++++++++++++++++++++++++++++- target/riscv/cpu_cfg.h | 2 +- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 15 +++++++------- target/riscv/tcg/tcg-cpu.c | 2 +- 5 files changed, 50 insertions(+), 11 deletions(-)