Message ID | 20230925110747.534238-1-mchitale@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | Add epmp to extensions list and rename it to smepmp | expand |
On Mon, Sep 25, 2023 at 9:08 PM Mayuresh Chitale <mchitale@ventanamicro.com> wrote: > > From: Himanshu Chauhan <hchauhan@ventanamicro.com> > > Smepmp is a ratified extension which qemu refers to as epmp. > Rename epmp to smepmp and add it to extension list so that > it is added to the isa string. > > Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 9 +++++---- > target/riscv/cpu.h | 2 +- > target/riscv/csr.c | 6 +++--- > target/riscv/pmp.c | 12 ++++++------ > 4 files changed, 15 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index befa64528f..0fb01788e7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -126,6 +126,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > @@ -488,7 +489,7 @@ static void rv32_ibex_cpu_init(Object *obj) > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > #endif > - cpu->cfg.epmp = true; > + cpu->cfg.ext_smepmp = true; > } > > static void rv32_imafcu_nommu_cpu_init(Object *obj) > @@ -1198,12 +1199,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > - if (cpu->cfg.epmp && !cpu->cfg.pmp) { > + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { > /* > * Enhanced PMP should only be available > * on harts with PMP support > */ > - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > + error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); > return; > } > > @@ -1560,7 +1561,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), > > /* ePMP 0.9.3 */ Can you remove this comment? Alistair > - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false), > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), > DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de7e43126a..9b4b012896 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -434,6 +434,7 @@ struct RISCVCPUConfig { > bool ext_zvfh; > bool ext_zvfhmin; > bool ext_smaia; > + bool ext_smepmp; > bool ext_ssaia; > bool ext_sscofpmf; > bool rvv_ta_all_1s; > @@ -468,7 +469,6 @@ struct RISCVCPUConfig { > uint16_t cboz_blocksize; > bool mmu; > bool pmp; > - bool epmp; > bool debug; > bool misa_w; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 4451bd1263..d9ecc222e7 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -519,9 +519,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno) > return RISCV_EXCP_ILLEGAL_INST; > } > > -static RISCVException epmp(CPURISCVState *env, int csrno) > +static RISCVException smepmp(CPURISCVState *env, int csrno) > { > - if (riscv_cpu_cfg(env)->epmp) { > + if (riscv_cpu_cfg(env)->ext_smepmp) { > return RISCV_EXCP_NONE; > } > > @@ -4337,7 +4337,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, > > /* Physical Memory Protection */ > - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, > + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg, > .min_priv_ver = PRIV_VERSION_1_11_0 }, > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index 1f5aca42e8..f498e414f0 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) > if (pmp_index < MAX_RISCV_PMPS) { > bool locked = true; > > - if (riscv_cpu_cfg(env)->epmp) { > + if (riscv_cpu_cfg(env)->ext_smepmp) { > /* mseccfg.RLB is set */ > if (MSECCFG_RLB_ISSET(env)) { > locked = false; > @@ -243,7 +243,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, > { > bool ret; > > - if (riscv_cpu_cfg(env)->epmp) { > + if (riscv_cpu_cfg(env)->ext_smepmp) { > if (MSECCFG_MMWP_ISSET(env)) { > /* > * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set > @@ -354,9 +354,9 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > > /* > * Convert the PMP permissions to match the truth table in the > - * ePMP spec. > + * Smepmp spec. > */ > - const uint8_t epmp_operation = > + const uint8_t smepmp_operation = > ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | > ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | > (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | > @@ -381,7 +381,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > * If mseccfg.MML Bit set, do the enhanced pmp priv check > */ > if (mode == PRV_M) { > - switch (epmp_operation) { > + switch (smepmp_operation) { > case 0: > case 1: > case 4: > @@ -412,7 +412,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > g_assert_not_reached(); > } > } else { > - switch (epmp_operation) { > + switch (smepmp_operation) { > case 0: > case 8: > case 9: > -- > 2.34.1 > >
On Wed, Oct 11, 2023 at 8:45 AM Alistair Francis <alistair23@gmail.com> wrote: > > On Mon, Sep 25, 2023 at 9:08 PM Mayuresh Chitale > <mchitale@ventanamicro.com> wrote: > > > > From: Himanshu Chauhan <hchauhan@ventanamicro.com> > > > > Smepmp is a ratified extension which qemu refers to as epmp. > > Rename epmp to smepmp and add it to extension list so that > > it is added to the isa string. > > > > Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > --- > > target/riscv/cpu.c | 9 +++++---- > > target/riscv/cpu.h | 2 +- > > target/riscv/csr.c | 6 +++--- > > target/riscv/pmp.c | 12 ++++++------ > > 4 files changed, 15 insertions(+), 14 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index befa64528f..0fb01788e7 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -126,6 +126,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > > + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > > @@ -488,7 +489,7 @@ static void rv32_ibex_cpu_init(Object *obj) > > #ifndef CONFIG_USER_ONLY > > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > > #endif > > - cpu->cfg.epmp = true; > > + cpu->cfg.ext_smepmp = true; > > } > > > > static void rv32_imafcu_nommu_cpu_init(Object *obj) > > @@ -1198,12 +1199,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > } > > > > - if (cpu->cfg.epmp && !cpu->cfg.pmp) { > > + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { > > /* > > * Enhanced PMP should only be available > > * on harts with PMP support > > */ > > - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > > + error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); > > return; > > } > > > > @@ -1560,7 +1561,7 @@ static Property riscv_cpu_extensions[] = { > > DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), > > > > /* ePMP 0.9.3 */ > > Can you remove this comment? Ok. > > Alistair > > > - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false), > > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), > > DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index de7e43126a..9b4b012896 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -434,6 +434,7 @@ struct RISCVCPUConfig { > > bool ext_zvfh; > > bool ext_zvfhmin; > > bool ext_smaia; > > + bool ext_smepmp; > > bool ext_ssaia; > > bool ext_sscofpmf; > > bool rvv_ta_all_1s; > > @@ -468,7 +469,6 @@ struct RISCVCPUConfig { > > uint16_t cboz_blocksize; > > bool mmu; > > bool pmp; > > - bool epmp; > > bool debug; > > bool misa_w; > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 4451bd1263..d9ecc222e7 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -519,9 +519,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno) > > return RISCV_EXCP_ILLEGAL_INST; > > } > > > > -static RISCVException epmp(CPURISCVState *env, int csrno) > > +static RISCVException smepmp(CPURISCVState *env, int csrno) > > { > > - if (riscv_cpu_cfg(env)->epmp) { > > + if (riscv_cpu_cfg(env)->ext_smepmp) { > > return RISCV_EXCP_NONE; > > } > > > > @@ -4337,7 +4337,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, > > > > /* Physical Memory Protection */ > > - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, > > + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg, > > .min_priv_ver = PRIV_VERSION_1_11_0 }, > > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, > > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > > index 1f5aca42e8..f498e414f0 100644 > > --- a/target/riscv/pmp.c > > +++ b/target/riscv/pmp.c > > @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) > > if (pmp_index < MAX_RISCV_PMPS) { > > bool locked = true; > > > > - if (riscv_cpu_cfg(env)->epmp) { > > + if (riscv_cpu_cfg(env)->ext_smepmp) { > > /* mseccfg.RLB is set */ > > if (MSECCFG_RLB_ISSET(env)) { > > locked = false; > > @@ -243,7 +243,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, > > { > > bool ret; > > > > - if (riscv_cpu_cfg(env)->epmp) { > > + if (riscv_cpu_cfg(env)->ext_smepmp) { > > if (MSECCFG_MMWP_ISSET(env)) { > > /* > > * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set > > @@ -354,9 +354,9 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > > > > /* > > * Convert the PMP permissions to match the truth table in the > > - * ePMP spec. > > + * Smepmp spec. > > */ > > - const uint8_t epmp_operation = > > + const uint8_t smepmp_operation = > > ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | > > ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | > > (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | > > @@ -381,7 +381,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > > * If mseccfg.MML Bit set, do the enhanced pmp priv check > > */ > > if (mode == PRV_M) { > > - switch (epmp_operation) { > > + switch (smepmp_operation) { > > case 0: > > case 1: > > case 4: > > @@ -412,7 +412,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > > g_assert_not_reached(); > > } > > } else { > > - switch (epmp_operation) { > > + switch (smepmp_operation) { > > case 0: > > case 8: > > case 9: > > -- > > 2.34.1 > > > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index befa64528f..0fb01788e7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -126,6 +126,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -488,7 +489,7 @@ static void rv32_ibex_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif - cpu->cfg.epmp = true; + cpu->cfg.ext_smepmp = true; } static void rv32_imafcu_nommu_cpu_init(Object *obj) @@ -1198,12 +1199,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available * on harts with PMP support */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); return; } @@ -1560,7 +1561,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), /* ePMP 0.9.3 */ - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..9b4b012896 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -434,6 +434,7 @@ struct RISCVCPUConfig { bool ext_zvfh; bool ext_zvfhmin; bool ext_smaia; + bool ext_smepmp; bool ext_ssaia; bool ext_sscofpmf; bool rvv_ta_all_1s; @@ -468,7 +469,6 @@ struct RISCVCPUConfig { uint16_t cboz_blocksize; bool mmu; bool pmp; - bool epmp; bool debug; bool misa_w; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4451bd1263..d9ecc222e7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -519,9 +519,9 @@ static RISCVException pmp(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } -static RISCVException epmp(CPURISCVState *env, int csrno) +static RISCVException smepmp(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->epmp) { + if (riscv_cpu_cfg(env)->ext_smepmp) { return RISCV_EXCP_NONE; } @@ -4337,7 +4337,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, /* Physical Memory Protection */ - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, + [CSR_MSECCFG] = { "mseccfg", smepmp, read_mseccfg, write_mseccfg, .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 1f5aca42e8..f498e414f0 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (pmp_index < MAX_RISCV_PMPS) { bool locked = true; - if (riscv_cpu_cfg(env)->epmp) { + if (riscv_cpu_cfg(env)->ext_smepmp) { /* mseccfg.RLB is set */ if (MSECCFG_RLB_ISSET(env)) { locked = false; @@ -243,7 +243,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, { bool ret; - if (riscv_cpu_cfg(env)->epmp) { + if (riscv_cpu_cfg(env)->ext_smepmp) { if (MSECCFG_MMWP_ISSET(env)) { /* * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set @@ -354,9 +354,9 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, /* * Convert the PMP permissions to match the truth table in the - * ePMP spec. + * Smepmp spec. */ - const uint8_t epmp_operation = + const uint8_t smepmp_operation = ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | @@ -381,7 +381,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, * If mseccfg.MML Bit set, do the enhanced pmp priv check */ if (mode == PRV_M) { - switch (epmp_operation) { + switch (smepmp_operation) { case 0: case 1: case 4: @@ -412,7 +412,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, g_assert_not_reached(); } } else { - switch (epmp_operation) { + switch (smepmp_operation) { case 0: case 8: case 9: