| Message ID | 20230920112020.651006-3-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: split TCG/KVM accelerators from cpu.c | expand |
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different > realize() path during the common riscv_cpu_realize(), making it a good > choice to start moving TCG exclusive code to tcg-cpu.c. > > Rename it to tcg_cpu_realizefn() and assign it as a implementation of > accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during > riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar > approach with KVM in the near future. > > riscv_cpu_validate_set_extensions() is too big and with too many > dependencies to be moved in this same patch. We'll do that next. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > --- > target/riscv/cpu.c | 128 ----------------------------------- > target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++ > 2 files changed, 133 insertions(+), 128 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e72c49c881..030629294f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -23,9 +23,7 @@ > #include "qemu/log.h" > #include "cpu.h" > #include "cpu_vendorid.h" > -#include "pmu.h" > #include "internals.h" > -#include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > #include "qapi/visitor.h" > @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > } > } > > -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) > -{ > - CPURISCVState *env = &cpu->env; > - int priv_version = -1; > - > - if (cpu->cfg.priv_spec) { > - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { > - priv_version = PRIV_VERSION_1_12_0; > - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > - priv_version = PRIV_VERSION_1_11_0; > - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > - priv_version = PRIV_VERSION_1_10_0; > - } else { > - error_setg(errp, > - "Unsupported privilege spec version '%s'", > - cpu->cfg.priv_spec); > - return; > - } > - > - env->priv_ver = priv_version; > - } > -} > - > static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > { > CPURISCVState *env = &cpu->env; > @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > } > } > > -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) > -{ > - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); > - CPUClass *cc = CPU_CLASS(mcc); > - CPURISCVState *env = &cpu->env; > - > - /* Validate that MISA_MXL is set properly. */ > - switch (env->misa_mxl_max) { > -#ifdef TARGET_RISCV64 > - case MXL_RV64: > - case MXL_RV128: > - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; > - break; > -#endif > - case MXL_RV32: > - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; > - break; > - default: > - g_assert_not_reached(); > - } > - > - if (env->misa_mxl_max != env->misa_mxl) { > - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); > - return; > - } > -} > - > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly. > @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > #endif > } > > -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) > -{ > - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { > - error_setg(errp, "H extension requires priv spec 1.12.0"); > - return; > - } > -} > - > -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) > -{ > - RISCVCPU *cpu = RISCV_CPU(dev); > - CPURISCVState *env = &cpu->env; > - Error *local_err = NULL; > - > - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { > - error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); > - return; > - } > - > - riscv_cpu_validate_misa_mxl(cpu, &local_err); > - if (local_err != NULL) { > - error_propagate(errp, local_err); > - return; > - } > - > - riscv_cpu_validate_priv_spec(cpu, &local_err); > - if (local_err != NULL) { > - error_propagate(errp, local_err); > - return; > - } > - > - riscv_cpu_validate_misa_priv(env, &local_err); > - if (local_err != NULL) { > - error_propagate(errp, local_err); > - return; > - } > - > - if (cpu->cfg.epmp && !cpu->cfg.pmp) { > - /* > - * Enhanced PMP should only be available > - * on harts with PMP support > - */ > - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > - return; > - } > - > - riscv_cpu_validate_set_extensions(cpu, &local_err); > - if (local_err != NULL) { > - error_propagate(errp, local_err); > - return; > - } > - > -#ifndef CONFIG_USER_ONLY > - CPU(dev)->tcg_cflags |= CF_PCREL; > - > - if (cpu->cfg.ext_sstc) { > - riscv_timer_init(cpu); > - } > - > - if (cpu->cfg.pmu_num) { > - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { > - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, > - riscv_pmu_timer_cb, cpu); > - } > - } > -#endif > -} > - > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > - if (tcg_enabled()) { > - riscv_cpu_realize_tcg(dev, &local_err); > - if (local_err != NULL) { > - error_propagate(errp, local_err); > - return; > - } > - } > - > riscv_cpu_finalize_features(cpu, &local_err); > if (local_err != NULL) { > error_propagate(errp, local_err); > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 0326cead0d..f47dc2064f 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -18,10 +18,142 @@ > */ I do think we should keep the Copyright statements from cpu.c in this new file as you are now copying across the majority of code from there Alistair > > #include "qemu/osdep.h" > +#include "exec/exec-all.h" > #include "cpu.h" > +#include "pmu.h" > +#include "time_helper.h" > +#include "qapi/error.h" > #include "qemu/accel.h" > #include "hw/core/accel-cpu.h" > > + > +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) > +{ > + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { > + error_setg(errp, "H extension requires priv spec 1.12.0"); > + return; > + } > +} > + > +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) > +{ > + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); > + CPUClass *cc = CPU_CLASS(mcc); > + CPURISCVState *env = &cpu->env; > + > + /* Validate that MISA_MXL is set properly. */ > + switch (env->misa_mxl_max) { > +#ifdef TARGET_RISCV64 > + case MXL_RV64: > + case MXL_RV128: > + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; > + break; > +#endif > + case MXL_RV32: > + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; > + break; > + default: > + g_assert_not_reached(); > + } > + > + if (env->misa_mxl_max != env->misa_mxl) { > + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); > + return; > + } > +} > + > +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) > +{ > + CPURISCVState *env = &cpu->env; > + int priv_version = -1; > + > + if (cpu->cfg.priv_spec) { > + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { > + priv_version = PRIV_VERSION_1_12_0; > + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > + priv_version = PRIV_VERSION_1_11_0; > + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > + priv_version = PRIV_VERSION_1_10_0; > + } else { > + error_setg(errp, > + "Unsupported privilege spec version '%s'", > + cpu->cfg.priv_spec); > + return; > + } > + > + env->priv_ver = priv_version; > + } > +} > + > +/* > + * We'll get here via the following path: > + * > + * riscv_cpu_realize() > + * -> cpu_exec_realizefn() > + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn()) > + */ > +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) > +{ > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + Error *local_err = NULL; > + > + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { > + error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); > + return false; > + } > + > + riscv_cpu_validate_misa_mxl(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return false; > + } > + > + riscv_cpu_validate_priv_spec(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return false; > + } > + > + riscv_cpu_validate_misa_priv(env, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return false; > + } > + > + if (cpu->cfg.epmp && !cpu->cfg.pmp) { > + /* > + * Enhanced PMP should only be available > + * on harts with PMP support > + */ > + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > + return false; > + } > + > + riscv_cpu_validate_set_extensions(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return false; > + } > + > +#ifndef CONFIG_USER_ONLY > + CPU(cs)->tcg_cflags |= CF_PCREL; > + > + if (cpu->cfg.ext_sstc) { > + riscv_timer_init(cpu); > + } > + > + if (cpu->cfg.pmu_num) { > + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { > + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + riscv_pmu_timer_cb, cpu); > + } > + } > +#endif > + > + return true; > +} > + > static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) > { > /* > @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) > AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); > > acc->cpu_class_init = tcg_cpu_class_init; > + acc->cpu_realizefn = tcg_cpu_realizefn; > } > > static const TypeInfo tcg_cpu_accel_type_info = { > -- > 2.41.0 > >
On 9/22/23 02:29, Alistair Francis wrote: > On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza > <dbarboza@ventanamicro.com> wrote: >> >> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different >> realize() path during the common riscv_cpu_realize(), making it a good >> choice to start moving TCG exclusive code to tcg-cpu.c. >> >> Rename it to tcg_cpu_realizefn() and assign it as a implementation of >> accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during >> riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar >> approach with KVM in the near future. >> >> riscv_cpu_validate_set_extensions() is too big and with too many >> dependencies to be moved in this same patch. We'll do that next. >> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> >> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> >> --- >> target/riscv/cpu.c | 128 ----------------------------------- >> target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++ >> 2 files changed, 133 insertions(+), 128 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index e72c49c881..030629294f 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -23,9 +23,7 @@ >> #include "qemu/log.h" >> #include "cpu.h" >> #include "cpu_vendorid.h" >> -#include "pmu.h" >> #include "internals.h" >> -#include "time_helper.h" >> #include "exec/exec-all.h" >> #include "qapi/error.h" >> #include "qapi/visitor.h" >> @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, >> } >> } >> >> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) >> -{ >> - CPURISCVState *env = &cpu->env; >> - int priv_version = -1; >> - >> - if (cpu->cfg.priv_spec) { >> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { >> - priv_version = PRIV_VERSION_1_12_0; >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { >> - priv_version = PRIV_VERSION_1_11_0; >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { >> - priv_version = PRIV_VERSION_1_10_0; >> - } else { >> - error_setg(errp, >> - "Unsupported privilege spec version '%s'", >> - cpu->cfg.priv_spec); >> - return; >> - } >> - >> - env->priv_ver = priv_version; >> - } >> -} >> - >> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) >> { >> CPURISCVState *env = &cpu->env; >> @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) >> } >> } >> >> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) >> -{ >> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); >> - CPUClass *cc = CPU_CLASS(mcc); >> - CPURISCVState *env = &cpu->env; >> - >> - /* Validate that MISA_MXL is set properly. */ >> - switch (env->misa_mxl_max) { >> -#ifdef TARGET_RISCV64 >> - case MXL_RV64: >> - case MXL_RV128: >> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; >> - break; >> -#endif >> - case MXL_RV32: >> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; >> - break; >> - default: >> - g_assert_not_reached(); >> - } >> - >> - if (env->misa_mxl_max != env->misa_mxl) { >> - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); >> - return; >> - } >> -} >> - >> /* >> * Check consistency between chosen extensions while setting >> * cpu->cfg accordingly. >> @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) >> #endif >> } >> >> -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) >> -{ >> - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { >> - error_setg(errp, "H extension requires priv spec 1.12.0"); >> - return; >> - } >> -} >> - >> -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) >> -{ >> - RISCVCPU *cpu = RISCV_CPU(dev); >> - CPURISCVState *env = &cpu->env; >> - Error *local_err = NULL; >> - >> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { >> - error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); >> - return; >> - } >> - >> - riscv_cpu_validate_misa_mxl(cpu, &local_err); >> - if (local_err != NULL) { >> - error_propagate(errp, local_err); >> - return; >> - } >> - >> - riscv_cpu_validate_priv_spec(cpu, &local_err); >> - if (local_err != NULL) { >> - error_propagate(errp, local_err); >> - return; >> - } >> - >> - riscv_cpu_validate_misa_priv(env, &local_err); >> - if (local_err != NULL) { >> - error_propagate(errp, local_err); >> - return; >> - } >> - >> - if (cpu->cfg.epmp && !cpu->cfg.pmp) { >> - /* >> - * Enhanced PMP should only be available >> - * on harts with PMP support >> - */ >> - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); >> - return; >> - } >> - >> - riscv_cpu_validate_set_extensions(cpu, &local_err); >> - if (local_err != NULL) { >> - error_propagate(errp, local_err); >> - return; >> - } >> - >> -#ifndef CONFIG_USER_ONLY >> - CPU(dev)->tcg_cflags |= CF_PCREL; >> - >> - if (cpu->cfg.ext_sstc) { >> - riscv_timer_init(cpu); >> - } >> - >> - if (cpu->cfg.pmu_num) { >> - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { >> - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, >> - riscv_pmu_timer_cb, cpu); >> - } >> - } >> -#endif >> -} >> - >> static void riscv_cpu_realize(DeviceState *dev, Error **errp) >> { >> CPUState *cs = CPU(dev); >> @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) >> return; >> } >> >> - if (tcg_enabled()) { >> - riscv_cpu_realize_tcg(dev, &local_err); >> - if (local_err != NULL) { >> - error_propagate(errp, local_err); >> - return; >> - } >> - } >> - >> riscv_cpu_finalize_features(cpu, &local_err); >> if (local_err != NULL) { >> error_propagate(errp, local_err); >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c >> index 0326cead0d..f47dc2064f 100644 >> --- a/target/riscv/tcg/tcg-cpu.c >> +++ b/target/riscv/tcg/tcg-cpu.c >> @@ -18,10 +18,142 @@ >> */ > > I do think we should keep the Copyright statements from cpu.c in this > new file as you are now copying across the majority of code from there I don't mind keeping the copyright statements from cpu.c here. Feel free to change it in tree (or let me know if you want me to re-send). Thanks, Daniel > > Alistair > >> >> #include "qemu/osdep.h" >> +#include "exec/exec-all.h" >> #include "cpu.h" >> +#include "pmu.h" >> +#include "time_helper.h" >> +#include "qapi/error.h" >> #include "qemu/accel.h" >> #include "hw/core/accel-cpu.h" >> >> + >> +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) >> +{ >> + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { >> + error_setg(errp, "H extension requires priv spec 1.12.0"); >> + return; >> + } >> +} >> + >> +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) >> +{ >> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); >> + CPUClass *cc = CPU_CLASS(mcc); >> + CPURISCVState *env = &cpu->env; >> + >> + /* Validate that MISA_MXL is set properly. */ >> + switch (env->misa_mxl_max) { >> +#ifdef TARGET_RISCV64 >> + case MXL_RV64: >> + case MXL_RV128: >> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; >> + break; >> +#endif >> + case MXL_RV32: >> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; >> + break; >> + default: >> + g_assert_not_reached(); >> + } >> + >> + if (env->misa_mxl_max != env->misa_mxl) { >> + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); >> + return; >> + } >> +} >> + >> +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) >> +{ >> + CPURISCVState *env = &cpu->env; >> + int priv_version = -1; >> + >> + if (cpu->cfg.priv_spec) { >> + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { >> + priv_version = PRIV_VERSION_1_12_0; >> + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { >> + priv_version = PRIV_VERSION_1_11_0; >> + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { >> + priv_version = PRIV_VERSION_1_10_0; >> + } else { >> + error_setg(errp, >> + "Unsupported privilege spec version '%s'", >> + cpu->cfg.priv_spec); >> + return; >> + } >> + >> + env->priv_ver = priv_version; >> + } >> +} >> + >> +/* >> + * We'll get here via the following path: >> + * >> + * riscv_cpu_realize() >> + * -> cpu_exec_realizefn() >> + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn()) >> + */ >> +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) >> +{ >> + RISCVCPU *cpu = RISCV_CPU(cs); >> + CPURISCVState *env = &cpu->env; >> + Error *local_err = NULL; >> + >> + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { >> + error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); >> + return false; >> + } >> + >> + riscv_cpu_validate_misa_mxl(cpu, &local_err); >> + if (local_err != NULL) { >> + error_propagate(errp, local_err); >> + return false; >> + } >> + >> + riscv_cpu_validate_priv_spec(cpu, &local_err); >> + if (local_err != NULL) { >> + error_propagate(errp, local_err); >> + return false; >> + } >> + >> + riscv_cpu_validate_misa_priv(env, &local_err); >> + if (local_err != NULL) { >> + error_propagate(errp, local_err); >> + return false; >> + } >> + >> + if (cpu->cfg.epmp && !cpu->cfg.pmp) { >> + /* >> + * Enhanced PMP should only be available >> + * on harts with PMP support >> + */ >> + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); >> + return false; >> + } >> + >> + riscv_cpu_validate_set_extensions(cpu, &local_err); >> + if (local_err != NULL) { >> + error_propagate(errp, local_err); >> + return false; >> + } >> + >> +#ifndef CONFIG_USER_ONLY >> + CPU(cs)->tcg_cflags |= CF_PCREL; >> + >> + if (cpu->cfg.ext_sstc) { >> + riscv_timer_init(cpu); >> + } >> + >> + if (cpu->cfg.pmu_num) { >> + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { >> + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, >> + riscv_pmu_timer_cb, cpu); >> + } >> + } >> +#endif >> + >> + return true; >> +} >> + >> static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) >> { >> /* >> @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) >> AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); >> >> acc->cpu_class_init = tcg_cpu_class_init; >> + acc->cpu_realizefn = tcg_cpu_realizefn; >> } >> >> static const TypeInfo tcg_cpu_accel_type_info = { >> -- >> 2.41.0 >> >>
On Mon, Sep 25, 2023 at 7:17 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > > > On 9/22/23 02:29, Alistair Francis wrote: > > On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza > > <dbarboza@ventanamicro.com> wrote: > >> > >> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different > >> realize() path during the common riscv_cpu_realize(), making it a good > >> choice to start moving TCG exclusive code to tcg-cpu.c. > >> > >> Rename it to tcg_cpu_realizefn() and assign it as a implementation of > >> accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during > >> riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar > >> approach with KVM in the near future. > >> > >> riscv_cpu_validate_set_extensions() is too big and with too many > >> dependencies to be moved in this same patch. We'll do that next. > >> > >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > >> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > >> --- > >> target/riscv/cpu.c | 128 ----------------------------------- > >> target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++ > >> 2 files changed, 133 insertions(+), 128 deletions(-) > >> > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index e72c49c881..030629294f 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -23,9 +23,7 @@ > >> #include "qemu/log.h" > >> #include "cpu.h" > >> #include "cpu_vendorid.h" > >> -#include "pmu.h" > >> #include "internals.h" > >> -#include "time_helper.h" > >> #include "exec/exec-all.h" > >> #include "qapi/error.h" > >> #include "qapi/visitor.h" > >> @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > >> } > >> } > >> > >> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) > >> -{ > >> - CPURISCVState *env = &cpu->env; > >> - int priv_version = -1; > >> - > >> - if (cpu->cfg.priv_spec) { > >> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { > >> - priv_version = PRIV_VERSION_1_12_0; > >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > >> - priv_version = PRIV_VERSION_1_11_0; > >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > >> - priv_version = PRIV_VERSION_1_10_0; > >> - } else { > >> - error_setg(errp, > >> - "Unsupported privilege spec version '%s'", > >> - cpu->cfg.priv_spec); > >> - return; > >> - } > >> - > >> - env->priv_ver = priv_version; > >> - } > >> -} > >> - > >> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > >> { > >> CPURISCVState *env = &cpu->env; > >> @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > >> } > >> } > >> > >> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) > >> -{ > >> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); > >> - CPUClass *cc = CPU_CLASS(mcc); > >> - CPURISCVState *env = &cpu->env; > >> - > >> - /* Validate that MISA_MXL is set properly. */ > >> - switch (env->misa_mxl_max) { > >> -#ifdef TARGET_RISCV64 > >> - case MXL_RV64: > >> - case MXL_RV128: > >> - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; > >> - break; > >> -#endif > >> - case MXL_RV32: > >> - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; > >> - break; > >> - default: > >> - g_assert_not_reached(); > >> - } > >> - > >> - if (env->misa_mxl_max != env->misa_mxl) { > >> - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); > >> - return; > >> - } > >> -} > >> - > >> /* > >> * Check consistency between chosen extensions while setting > >> * cpu->cfg accordingly. > >> @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > >> #endif > >> } > >> > >> -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) > >> -{ > >> - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { > >> - error_setg(errp, "H extension requires priv spec 1.12.0"); > >> - return; > >> - } > >> -} > >> - > >> -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) > >> -{ > >> - RISCVCPU *cpu = RISCV_CPU(dev); > >> - CPURISCVState *env = &cpu->env; > >> - Error *local_err = NULL; > >> - > >> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { > >> - error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_misa_mxl(cpu, &local_err); > >> - if (local_err != NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_priv_spec(cpu, &local_err); > >> - if (local_err != NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_misa_priv(env, &local_err); > >> - if (local_err != NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> - if (cpu->cfg.epmp && !cpu->cfg.pmp) { > >> - /* > >> - * Enhanced PMP should only be available > >> - * on harts with PMP support > >> - */ > >> - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_set_extensions(cpu, &local_err); > >> - if (local_err != NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> -#ifndef CONFIG_USER_ONLY > >> - CPU(dev)->tcg_cflags |= CF_PCREL; > >> - > >> - if (cpu->cfg.ext_sstc) { > >> - riscv_timer_init(cpu); > >> - } > >> - > >> - if (cpu->cfg.pmu_num) { > >> - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { > >> - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, > >> - riscv_pmu_timer_cb, cpu); > >> - } > >> - } > >> -#endif > >> -} > >> - > >> static void riscv_cpu_realize(DeviceState *dev, Error **errp) > >> { > >> CPUState *cs = CPU(dev); > >> @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > >> return; > >> } > >> > >> - if (tcg_enabled()) { > >> - riscv_cpu_realize_tcg(dev, &local_err); > >> - if (local_err != NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - } > >> - > >> riscv_cpu_finalize_features(cpu, &local_err); > >> if (local_err != NULL) { > >> error_propagate(errp, local_err); > >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > >> index 0326cead0d..f47dc2064f 100644 > >> --- a/target/riscv/tcg/tcg-cpu.c > >> +++ b/target/riscv/tcg/tcg-cpu.c > >> @@ -18,10 +18,142 @@ > >> */ > > > > I do think we should keep the Copyright statements from cpu.c in this > > new file as you are now copying across the majority of code from there > > I don't mind keeping the copyright statements from cpu.c here. Feel free to change it > in tree (or let me know if you want me to re-send). Whoops. I missed this comment. Do you mind sending a v4 then I will apply that Alistair
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e72c49c881..030629294f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,9 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "pmu.h" #include "internals.h" -#include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, } } -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env = &cpu->env; - int priv_version = -1; - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version = PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version = PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version = PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - - env->priv_ver = priv_version; - } -} - static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env = &cpu->env; @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) -{ - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc = CPU_CLASS(mcc); - CPURISCVState *env = &cpu->env; - - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - - if (env->misa_mxl_max != env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } -} - /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) #endif } -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) -{ - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { - error_setg(errp, "H extension requires priv spec 1.12.0"); - return; - } -} - -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) -{ - RISCVCPU *cpu = RISCV_CPU(dev); - CPURISCVState *env = &cpu->env; - Error *local_err = NULL; - - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { - error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); - return; - } - - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_misa_priv(env, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } - - riscv_cpu_validate_set_extensions(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - -#ifndef CONFIG_USER_ONLY - CPU(dev)->tcg_cflags |= CF_PCREL; - - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } - - if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_pmu_timer_cb, cpu); - } - } -#endif -} - static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (tcg_enabled()) { - riscv_cpu_realize_tcg(dev, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - } - riscv_cpu_finalize_features(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 0326cead0d..f47dc2064f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -18,10 +18,142 @@ */ #include "qemu/osdep.h" +#include "exec/exec-all.h" #include "cpu.h" +#include "pmu.h" +#include "time_helper.h" +#include "qapi/error.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" + +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc = CPU_CLASS(mcc); + CPURISCVState *env = &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max != env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env = &cpu->env; + int priv_version = -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version = PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version = PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver = priv_version; + } +} + +/* + * We'll get here via the following path: + * + * riscv_cpu_realize() + * -> cpu_exec_realizefn() + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn()) + */ +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + Error *local_err = NULL; + + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { + error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); + return false; + } + + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return false; + } + + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return false; + } + + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return false; + } + +#ifndef CONFIG_USER_ONLY + CPU(cs)->tcg_cflags |= CF_PCREL; + + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif + + return true; +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); acc->cpu_class_init = tcg_cpu_class_init; + acc->cpu_realizefn = tcg_cpu_realizefn; } static const TypeInfo tcg_cpu_accel_type_info = {