Message ID | 20230920112020.651006-14-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: split TCG/KVM accelerators from cpu.c | expand |
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > riscv_cpu_add_misa_properties() is being used to fill the missing KVM > MISA properties but it is a TCG helper that was adapted to do so. We'll > move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill > the remaining MISA properties on its own. > > Do not use riscv_cpu_add_misa_properties(). Let's create a new array > with all available MISA bits we support that can be read by KVM. The > array is zero terminate to allow us to iterate through it without > knowing its size. > > Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM > MISA properties as usual and then use this array to add any missing MISA > properties with the riscv_cpu_add_kvm_unavail_prop() helper. > > Note that we're creating misa_bits[], and not using the existing > 'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa > related functions and it doesn't have all MISA bits we support. Commit > 0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the > full context. > > While we're at it, move both satp and the multi-letter extension > properties to kvm_riscv_add_cpu_user_properties() as well. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 3 ++- > target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++-------- > 3 files changed, 18 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 51567c2f12..665c21af6a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -38,6 +38,8 @@ > > /* RISC-V CPU definitions */ > static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > +const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, > + RVC, RVS, RVU, RVH, RVJ, RVG, 0}; > > struct isa_ext_data { > const char *name; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index cb13464ba6..7235eafc1a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -43,7 +43,7 @@ > #define RV(x) ((target_ulong)1 << (x - 'A')) > > /* > - * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] > + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] > * when adding new MISA bits here. > */ > #define RVI RV('I') > @@ -60,6 +60,7 @@ > #define RVJ RV('J') > #define RVG RV('G') > > +extern const uint32_t misa_bits[]; > const char *riscv_get_misa_ext_name(uint32_t bit); > const char *riscv_get_misa_ext_description(uint32_t bit); > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 606fdab223..c6615cb807 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -396,6 +396,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > { > int i; > > + riscv_add_satp_mode_properties(cpu_obj); > + > for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { > KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; > int bit = misa_cfg->offset; > @@ -411,6 +413,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > misa_cfg->description); > } > > + for (i = 0; misa_bits[i] != 0; i++) { > + const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); > + riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); > + } > + > for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { > KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; > > @@ -427,6 +434,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) > object_property_add(cpu_obj, "cboz_blocksize", "uint16", > NULL, kvm_cpu_set_cbomz_blksize, > NULL, &kvm_cboz_blocksize); > + > + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); > + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); > + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); > } > > static int kvm_riscv_get_regs_core(CPUState *cs) > @@ -801,7 +812,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) > } > } > > -static void riscv_init_user_properties(Object *cpu_obj) > +static void riscv_init_kvm_registers(Object *cpu_obj) > { > RISCVCPU *cpu = RISCV_CPU(cpu_obj); > KVMScratchCPU kvmcpu; > @@ -810,7 +821,6 @@ static void riscv_init_user_properties(Object *cpu_obj) > return; > } > > - kvm_riscv_add_cpu_user_properties(cpu_obj); > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); > @@ -1324,13 +1334,9 @@ static void kvm_cpu_instance_init(CPUState *cs) > Object *obj = OBJECT(RISCV_CPU(cs)); > DeviceState *dev = DEVICE(obj); > > - riscv_init_user_properties(obj); > - riscv_add_satp_mode_properties(obj); > - riscv_cpu_add_misa_properties(obj); > + riscv_init_kvm_registers(obj); > > - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); > - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); > + kvm_riscv_add_cpu_user_properties(obj); > > for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { > /* Check if we have a specific KVM handler for the option */ > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 51567c2f12..665c21af6a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,6 +38,8 @@ /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; +const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, + RVC, RVS, RVU, RVH, RVJ, RVG, 0}; struct isa_ext_data { const char *name; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cb13464ba6..7235eafc1a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -43,7 +43,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) /* - * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] * when adding new MISA bits here. */ #define RVI RV('I') @@ -60,6 +60,7 @@ #define RVJ RV('J') #define RVG RV('G') +extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 606fdab223..c6615cb807 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -396,6 +396,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; + riscv_add_satp_mode_properties(cpu_obj); + for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; int bit = misa_cfg->offset; @@ -411,6 +413,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) misa_cfg->description); } + for (i = 0; misa_bits[i] != 0; i++) { + const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); + riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); + } + for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; @@ -427,6 +434,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); + + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); } static int kvm_riscv_get_regs_core(CPUState *cs) @@ -801,7 +812,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) } } -static void riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_kvm_registers(Object *cpu_obj) { RISCVCPU *cpu = RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -810,7 +821,6 @@ static void riscv_init_user_properties(Object *cpu_obj) return; } - kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); @@ -1324,13 +1334,9 @@ static void kvm_cpu_instance_init(CPUState *cs) Object *obj = OBJECT(RISCV_CPU(cs)); DeviceState *dev = DEVICE(obj); - riscv_init_user_properties(obj); - riscv_add_satp_mode_properties(obj); - riscv_cpu_add_misa_properties(obj); + riscv_init_kvm_registers(obj); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); + kvm_riscv_add_cpu_user_properties(obj); for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { /* Check if we have a specific KVM handler for the option */