| Message ID | 20230727220927.62950-10-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: add 'max' CPU, deprecate 'any' | expand |
On 2023/7/28 06:09, Daniel Henrique Barboza wrote: > Inside riscv_cpu_validate_v() we're always throwing a log message if the > user didn't set a vector version via 'vext_spec'. > > We're going to include one case with the 'max' CPU where env->vext_ver > will be set in the cpu_init(). But that alone will not stop the "vector > version is not specified" message from appearing. The usefulness of this > log message is debatable for the generic CPUs, but for a 'max' CPU type, > where we are supposed to deliver a CPU model with all features possible, > it's strange to force users to set 'vext_spec' to get rid of this > message. > > Change riscv_cpu_validate_v() to not throw this log message if > env->vext_ver is already set. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > target/riscv/cpu.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 08f61ed051..01b0d228f5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -939,8 +939,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > Error **errp) > { > - int vext_version = VEXT_VERSION_1_00_0; > - > if (!is_power_of_2(cfg->vlen)) { > error_setg(errp, "Vector extension VLEN must be power of 2"); > return; > @@ -963,17 +961,18 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > } > if (cfg->vext_spec) { > if (!g_strcmp0(cfg->vext_spec, "v1.0")) { > - vext_version = VEXT_VERSION_1_00_0; > + env->vext_ver = VEXT_VERSION_1_00_0; > } else { > error_setg(errp, "Unsupported vector spec version '%s'", > cfg->vext_spec); > return; > } > - } else { > + } else if (env->vext_ver == 0) { > qemu_log("vector version is not specified, " > "use the default value v1.0\n"); > + > + env->vext_ver = VEXT_VERSION_1_00_0; > } > - env->vext_ver = vext_version; > } > > static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
On Thu, Jul 27, 2023 at 6:22 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Inside riscv_cpu_validate_v() we're always throwing a log message if the > user didn't set a vector version via 'vext_spec'. > > We're going to include one case with the 'max' CPU where env->vext_ver > will be set in the cpu_init(). But that alone will not stop the "vector > version is not specified" message from appearing. The usefulness of this > log message is debatable for the generic CPUs, but for a 'max' CPU type, > where we are supposed to deliver a CPU model with all features possible, > it's strange to force users to set 'vext_spec' to get rid of this > message. > > Change riscv_cpu_validate_v() to not throw this log message if > env->vext_ver is already set. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 08f61ed051..01b0d228f5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -939,8 +939,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > Error **errp) > { > - int vext_version = VEXT_VERSION_1_00_0; > - > if (!is_power_of_2(cfg->vlen)) { > error_setg(errp, "Vector extension VLEN must be power of 2"); > return; > @@ -963,17 +961,18 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > } > if (cfg->vext_spec) { > if (!g_strcmp0(cfg->vext_spec, "v1.0")) { > - vext_version = VEXT_VERSION_1_00_0; > + env->vext_ver = VEXT_VERSION_1_00_0; > } else { > error_setg(errp, "Unsupported vector spec version '%s'", > cfg->vext_spec); > return; > } > - } else { > + } else if (env->vext_ver == 0) { > qemu_log("vector version is not specified, " > "use the default value v1.0\n"); > + > + env->vext_ver = VEXT_VERSION_1_00_0; > } > - env->vext_ver = vext_version; > } > > static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08f61ed051..01b0d228f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -939,8 +939,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - int vext_version = VEXT_VERSION_1_00_0; - if (!is_power_of_2(cfg->vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); return; @@ -963,17 +961,18 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, } if (cfg->vext_spec) { if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - vext_version = VEXT_VERSION_1_00_0; + env->vext_ver = VEXT_VERSION_1_00_0; } else { error_setg(errp, "Unsupported vector spec version '%s'", cfg->vext_spec); return; } - } else { + } else if (env->vext_ver == 0) { qemu_log("vector version is not specified, " "use the default value v1.0\n"); + + env->vext_ver = VEXT_VERSION_1_00_0; } - env->vext_ver = vext_version; } static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
Inside riscv_cpu_validate_v() we're always throwing a log message if the user didn't set a vector version via 'vext_spec'. We're going to include one case with the 'max' CPU where env->vext_ver will be set in the cpu_init(). But that alone will not stop the "vector version is not specified" message from appearing. The usefulness of this log message is debatable for the generic CPUs, but for a 'max' CPU type, where we are supposed to deliver a CPU model with all features possible, it's strange to force users to set 'vext_spec' to get rid of this message. Change riscv_cpu_validate_v() to not throw this log message if env->vext_ver is already set. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)