| Message ID | 20230711165917.2629866-5-max.chou@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V vector cryptographic instruction set support | expand |
On Tue, Jul 11, 2023 at 1:00 PM Max Chou <max.chou@sifive.com> wrote: > > From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> > > This commit adds support for the Zvbc vector-crypto extension, which > consists of the following instructions: > > * vclmulh.[vx,vv] > * vclmul.[vx,vv] > > Translation functions are defined in > `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in > `target/riscv/vcrypto_helper.c`. > > Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > Co-authored-by: Max Chou <max.chou@sifive.com> > Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> > Signed-off-by: Max Chou <max.chou@sifive.com> > [max.chou@sifive.com: Exposed x-zvbc property] Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 9 ++++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/helper.h | 6 +++ > target/riscv/insn32.decode | 6 +++ > target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 1 + > target/riscv/vcrypto_helper.c | 59 ++++++++++++++++++++++ > 8 files changed, 146 insertions(+), 1 deletion(-) > create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc > create mode 100644 target/riscv/vcrypto_helper.c > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9339c0241d6..d1dc78d483f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), > ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), > ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), > + ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), > ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), > ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), > ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), > @@ -1268,6 +1269,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { > + error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions"); > + return; > + } > + > if (cpu->cfg.ext_zk) { > cpu->cfg.ext_zkn = true; > cpu->cfg.ext_zkr = true; > @@ -1845,6 +1851,9 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), > DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), > > + /* Vector cryptography extensions */ > + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), > + > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 2bd9510ba3e..d25b36a5128 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -85,6 +85,7 @@ struct RISCVCPUConfig { > bool ext_zve32f; > bool ext_zve64f; > bool ext_zve64d; > + bool ext_zvbc; > bool ext_zmmul; > bool ext_zvfbfmin; > bool ext_zvfbfwma; > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index c95adaf08ac..6776777c4eb 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1182,3 +1182,9 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32) > > DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) > + > +/* Vector crypto functions */ > +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index e341fa92139..dd50d5a48c7 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -946,3 +946,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm > # *** Zvfbfwma Standard Extension *** > vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm > vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm > + > +# *** Zvbc vector crypto extension *** > +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm > +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm > +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm > +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm > diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc > new file mode 100644 > index 00000000000..552b08a2fd1 > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvvk.c.inc > @@ -0,0 +1,62 @@ > +/* > + * RISC-V translation routines for the vector crypto extension. > + * > + * Copyright (C) 2023 SiFive, Inc. > + * Written by Codethink Ltd and SiFive. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +/* > + * Zvbc > + */ > + > +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ > + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > + { \ > + if (CHECK(s, a)) { \ > + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ > + gen_helper_##NAME, s); \ > + } \ > + return false; \ > + } > + > +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) > +{ > + return opivv_check(s, a) && > + s->cfg_ptr->ext_zvbc == true && > + s->sew == MO_64; > +} > + > +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) > +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) > + > +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ > + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > + { \ > + if (CHECK(s, a)) { \ > + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ > + gen_helper_##NAME, s); \ > + } \ > + return false; \ > + } > + > +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) > +{ > + return opivx_check(s, a) && > + s->cfg_ptr->ext_zvbc == true && > + s->sew == MO_64; > +} > + > +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) > +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > index c3801ee5e04..660078bda1f 100644 > --- a/target/riscv/meson.build > +++ b/target/riscv/meson.build > @@ -21,7 +21,8 @@ riscv_ss.add(files( > 'translate.c', > 'm128_helper.c', > 'crypto_helper.c', > - 'zce_helper.c' > + 'zce_helper.c', > + 'vcrypto_helper.c' > )) > riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 697df1be9e2..7dbf173adb5 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1094,6 +1094,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > #include "insn_trans/trans_rvzfa.c.inc" > #include "insn_trans/trans_rvzfh.c.inc" > #include "insn_trans/trans_rvk.c.inc" > +#include "insn_trans/trans_rvvk.c.inc" > #include "insn_trans/trans_privileged.c.inc" > #include "insn_trans/trans_svinval.c.inc" > #include "insn_trans/trans_rvbf16.c.inc" > diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c > new file mode 100644 > index 00000000000..8b7c63d4997 > --- /dev/null > +++ b/target/riscv/vcrypto_helper.c > @@ -0,0 +1,59 @@ > +/* > + * RISC-V Vector Crypto Extension Helpers for QEMU. > + * > + * Copyright (C) 2023 SiFive, Inc. > + * Written by Codethink Ltd and SiFive. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/host-utils.h" > +#include "qemu/bitops.h" > +#include "cpu.h" > +#include "exec/memop.h" > +#include "exec/exec-all.h" > +#include "exec/helper-proto.h" > +#include "internals.h" > +#include "vector_internals.h" > + > +static uint64_t clmul64(uint64_t y, uint64_t x) > +{ > + uint64_t result = 0; > + for (int j = 63; j >= 0; j--) { > + if ((y >> j) & 1) { > + result ^= (x << j); > + } > + } > + return result; > +} > + > +static uint64_t clmulh64(uint64_t y, uint64_t x) > +{ > + uint64_t result = 0; > + for (int j = 63; j >= 1; j--) { > + if ((y >> j) & 1) { > + result ^= (x >> (64 - j)); > + } > + } > + return result; > +} > + > +RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64) > +GEN_VEXT_VV(vclmul_vv, 8) > +RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64) > +GEN_VEXT_VX(vclmul_vx, 8) > +RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) > +GEN_VEXT_VV(vclmulh_vv, 8) > +RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) > +GEN_VEXT_VX(vclmulh_vx, 8) > -- > 2.34.1 >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d6..d1dc78d483f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), @@ -1268,6 +1269,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { + error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; @@ -1845,6 +1851,9 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), + /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3e..d25b36a5128 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -85,6 +85,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbc; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c95adaf08ac..6776777c4eb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1182,3 +1182,9 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) + +/* Vector crypto functions */ +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e341fa92139..dd50d5a48c7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -946,3 +946,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm # *** Zvfbfwma Standard Extension *** vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm + +# *** Zvbc vector crypto extension *** +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc new file mode 100644 index 00000000000..552b08a2fd1 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -0,0 +1,62 @@ +/* + * RISC-V translation routines for the vector crypto extension. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * Zvbc + */ + +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvbc == true && + s->sew == MO_64; +} + +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) + +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && + s->cfg_ptr->ext_zvbc == true && + s->sew == MO_64; +} + +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index c3801ee5e04..660078bda1f 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -21,7 +21,8 @@ riscv_ss.add(files( 'translate.c', 'm128_helper.c', 'crypto_helper.c', - 'zce_helper.c' + 'zce_helper.c', + 'vcrypto_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 697df1be9e2..7dbf173adb5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1094,6 +1094,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvzfa.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" +#include "insn_trans/trans_rvvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c new file mode 100644 index 00000000000..8b7c63d4997 --- /dev/null +++ b/target/riscv/vcrypto_helper.c @@ -0,0 +1,59 @@ +/* + * RISC-V Vector Crypto Extension Helpers for QEMU. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/memop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "internals.h" +#include "vector_internals.h" + +static uint64_t clmul64(uint64_t y, uint64_t x) +{ + uint64_t result = 0; + for (int j = 63; j >= 0; j--) { + if ((y >> j) & 1) { + result ^= (x << j); + } + } + return result; +} + +static uint64_t clmulh64(uint64_t y, uint64_t x) +{ + uint64_t result = 0; + for (int j = 63; j >= 1; j--) { + if ((y >> j) & 1) { + result ^= (x >> (64 - j)); + } + } + return result; +} + +RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64) +GEN_VEXT_VV(vclmul_vv, 8) +RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64) +GEN_VEXT_VX(vclmul_vx, 8) +RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) +GEN_VEXT_VV(vclmulh_vv, 8) +RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) +GEN_VEXT_VX(vclmulh_vx, 8)