[PULL,16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing

From: Bin Meng <bmeng@tinylab.org>

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bmeng@tinylab.org>,
 Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
 Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot
 testing
Date: Mon, 10 Jul 2023 22:31:27 +1000
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Message ID	20230710123205.2441106-17-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng <bmeng@tinylab.org>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing Date: Mon, 10 Jul 2023 22:31:27 +1000 Message-Id: <20230710123205.2441106-17-alistair.francis@wdc.com> In-Reply-To: <20230710123205.2441106-1-alistair.francis@wdc.com> References: <20230710123205.2441106-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=alistair23@gmail.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/54] target/riscv: Use xl instead of mxl for disassemble \| expand [PULL,01/54] target/riscv: Use xl instead of mxl for disassemble [PULL,02/54] target/riscv: Factor out extension tests to cpu_cfg.h [PULL,03/54] disas/riscv: Move types/constants to new header file [PULL,04/54] disas/riscv: Make rv_op_illegal a shared enum value [PULL,05/54] disas/riscv: Encapsulate opcode_data into decode [PULL,06/54] disas/riscv: Provide infrastructure for vendor extensions [PULL,07/54] disas/riscv: Add support for XVentanaCondOps [PULL,08/54] disas/riscv: Add support for XThead* instructions [PULL,09/54] target/riscv: Make MPV only work when MPP != PRV_M [PULL,10/54] target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled [PULL,11/54] target/riscv: Remove redundant assignment to SXL [PULL,12/54] target/riscv/cpu.c: fix veyron-v1 CPU properties [PULL,13/54] target/riscv: Add additional xlen for address when MPRV=1 [PULL,14/54] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV [PULL,15/54] roms/opensbi: Upgrade from v1.2 to v1.3 [PULL,16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing [PULL,17/54] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b. [PULL,18/54] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. [PULL,19/54] tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e [PULL,20/54] target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson [PULL,21/54] target/riscv: Only build KVM guest with same wordsize as host [PULL,22/54] target/riscv: Add RVV registers to log [PULL,23/54] hw/riscv/virt: Restrict ACLINT to TCG [PULL,24/54] linux-user/riscv: Add syscall riscv_hwprobe [PULL,25/54] target/riscv: Add properties for BF16 extensions [PULL,26/54] target/riscv: Add support for Zfbfmin extension [PULL,27/54] target/riscv: Add support for Zvfbfmin extension [PULL,28/54] target/riscv: Add support for Zvfbfwma extension [PULL,29/54] target/riscv: Expose properties for BF16 extensions [PULL,30/54] target/riscv: Set the correct exception for implict G-stage translation fail [PULL,31/54] target/riscv: Add disas support for BF16 extensions [PULL,32/54] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly [PULL,33/54] riscv: Generate devicetree only after machine initialization is complete [PULL,34/54] hw/riscv: virt: Convert fdt_load_addr to uint64_t [PULL,35/54] target/riscv: skip features setup for KVM CPUs [PULL,36/54] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set [PULL,37/54] target/riscv/cpu.c: restrict 'mvendorid' value [PULL,38/54] target/riscv/cpu.c: restrict 'mimpid' value [PULL,39/54] target/riscv/cpu.c: restrict 'marchid' value [PULL,40/54] target/riscv: use KVM scratch CPUs to init KVM properties [PULL,41/54] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() [PULL,42/54] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs [PULL,43/54] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU [PULL,44/54] target/riscv/cpu: add misa_ext_info_arr[] [PULL,45/54] target/riscv: add KVM specific MISA properties [PULL,46/54] target/riscv/kvm.c: update KVM MISA bits [PULL,47/54] target/riscv/kvm.c: add multi-letter extension KVM properties [PULL,48/54] target/riscv/cpu.c: add satp_mode properties earlier [PULL,49/54] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() [PULL,50/54] target/riscv/cpu.c: create KVM mock properties [PULL,51/54] target/riscv: update multi-letter extension KVM properties [PULL,52/54] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper [PULL,53/54] target/riscv/kvm.c: read/write (cbom\|cboz)_blocksize in KVM [PULL,54/54] riscv: Add support for the Zfa extension

[PULL,16/54] tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing

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Patch