[PULL,05/60] target/riscv/cpu.c: remove set_priv_version()

Message ID	20230614012017.3100663-6-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Date: Wed, 14 Jun 2023 11:19:22 +1000 Message-Id: <20230614012017.3100663-6-alistair.francis@wdc.com> In-Reply-To: <20230614012017.3100663-1-alistair.francis@wdc.com> References: <20230614012017.3100663-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=alistair23@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero \| expand [PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero [PULL,02/60] target/riscv: Move zc* out of the experimental properties [PULL,03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() [PULL,04/60] target/riscv/cpu.c: remove set_vext_version() [PULL,05/60] target/riscv/cpu.c: remove set_priv_version() [PULL,06/60] target/riscv: add PRIV_VERSION_LATEST [PULL,07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv versi… [PULL,08/60] target/riscv: Update check for Zca/Zcf/Zcd [PULL,09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers [PULL,10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() [PULL,11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() [PULL,12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() [PULL,13/60] target/riscv: rework write_misa() [PULL,14/60] target/riscv: Update pmp_get_tlb_size() [PULL,15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp [PULL,16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs [PULL,17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool [PULL,18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled [PULL,19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() [PULL,20/60] target/riscv: Flush TLB when MMWP or MML bits are changed [PULL,21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() [PULL,22/60] target/riscv: Flush TLB when pmpaddr is updated [PULL,23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes [PULL,24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write [PULL,25/60] target/riscv: Deny access if access is partially inside the PMP entry [PULL,26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions [PULL,27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro [PULL,28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition [PULL,29/60] hw/riscv/opentitan: Explicit machine type definition [PULL,30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size [PULL,31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs [PULL,32/60] target/riscv: Fix pointer mask transformation for vector address [PULL,33/60] target/riscv: Update cur_pmmask/base when xl changes [PULL,34/60] target/riscv: smstateen check for fcsr [PULL,35/60] target/riscv: Reuse tb->flags.FS [PULL,36/60] target/riscv: smstateen knobs [PULL,37/60] disas: Change type of disassemble_info.target_info to pointer [PULL,38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h [PULL,39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info [PULL,40/60] disas/riscv.c: Support disas for Zcm* extensions [PULL,41/60] disas/riscv.c: Support disas for Z*inx extensions [PULL,42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions [PULL,43/60] disas/riscv.c: Fix lines with over 80 characters [PULL,44/60] disas/riscv.c: Remove redundant parentheses [PULL,45/60] target/riscv: Fix target address to update badaddr [PULL,46/60] target/riscv: Introduce cur_insn_len into DisasContext [PULL,47/60] target/riscv: Change gen_goto_tb to work on displacements [PULL,48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc [PULL,49/60] target/riscv: Use true diff for gen_pc_plus_diff [PULL,50/60] target/riscv: Enable PC-relative translation [PULL,51/60] target/riscv: Remove pc_succ_insn from DisasContext [PULL,52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" [PULL,53/60] riscv/virt: Support using pflash via -blockdev option [PULL,54/60] docs/system: riscv: Add pflash usage details [PULL,55/60] util/log: Add vector registers to log [PULL,56/60] target/riscv: Fix initialized value for cur_pmmask [PULL,57/60] target/riscv/vector_helper.c: clean up reference of MTYPE [PULL,58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements [PULL,59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP [PULL,60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.

Message ID

20230614012017.3100663-6-alistair.francis@wdc.com

State

New

Headers

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
 LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
 Weiwei Li <liweiwei@iscas.ac.cn>,
 Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 05/60] target/riscv/cpu.c: remove set_priv_version()
Date: Wed, 14 Jun 2023 11:19:22 +1000
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Series

[PULL,01/60] target/riscv/vector_helper.c: skip set tail when vta is zero | expand

Commit Message

Alistair Francis June 14, 2023, 1:19 a.m. UTC

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The setter is doing nothing special. Just set env->priv_ver directly.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 29 ++++++++++++-----------------
 1 file changed, 12 insertions(+), 17 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13d725dc20..9fc9d1cc0f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -247,11 +247,6 @@  static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
     env->misa_ext_mask = env->misa_ext = ext;
 }
 
-static void set_priv_version(CPURISCVState *env, int priv_ver)
-{
-    env->priv_ver = priv_ver;
-}
-
 #ifndef CONFIG_USER_ONLY
 static uint8_t satp_mode_from_str(const char *satp_mode_str)
 {
@@ -350,7 +345,7 @@  static void riscv_any_cpu_init(Object *obj)
         VM_1_10_SV32 : VM_1_10_SV57);
 #endif
 
-    set_priv_version(env, PRIV_VERSION_1_12_0);
+    env->priv_ver = PRIV_VERSION_1_12_0;
 }
 
 #if defined(TARGET_RISCV64)
@@ -361,7 +356,7 @@  static void rv64_base_cpu_init(Object *obj)
     set_misa(env, MXL_RV64, 0);
     riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
-    set_priv_version(env, PRIV_VERSION_1_12_0);
+    env->priv_ver = PRIV_VERSION_1_12_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
 #endif
@@ -371,7 +366,7 @@  static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-    set_priv_version(env, PRIV_VERSION_1_10_0);
+    env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
 #endif
@@ -383,7 +378,7 @@  static void rv64_sifive_e_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
-    set_priv_version(env, PRIV_VERSION_1_10_0);
+    env->priv_ver = PRIV_VERSION_1_10_0;
     cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -396,7 +391,7 @@  static void rv64_thead_c906_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
-    set_priv_version(env, PRIV_VERSION_1_11_0);
+    env->priv_ver = PRIV_VERSION_1_11_0;
 
     cpu->cfg.ext_zfh = true;
     cpu->cfg.mmu = true;
@@ -467,7 +462,7 @@  static void rv128_base_cpu_init(Object *obj)
     set_misa(env, MXL_RV128, 0);
     riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
-    set_priv_version(env, PRIV_VERSION_1_12_0);
+    env->priv_ver = PRIV_VERSION_1_12_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
 #endif
@@ -480,7 +475,7 @@  static void rv32_base_cpu_init(Object *obj)
     set_misa(env, MXL_RV32, 0);
     riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
-    set_priv_version(env, PRIV_VERSION_1_12_0);
+    env->priv_ver = PRIV_VERSION_1_12_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
 #endif
@@ -490,7 +485,7 @@  static void rv32_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-    set_priv_version(env, PRIV_VERSION_1_10_0);
+    env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
 #endif
@@ -502,7 +497,7 @@  static void rv32_sifive_e_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
-    set_priv_version(env, PRIV_VERSION_1_10_0);
+    env->priv_ver = PRIV_VERSION_1_10_0;
     cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -515,7 +510,7 @@  static void rv32_ibex_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
-    set_priv_version(env, PRIV_VERSION_1_11_0);
+    env->priv_ver = PRIV_VERSION_1_11_0;
     cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -529,7 +524,7 @@  static void rv32_imafcu_nommu_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
-    set_priv_version(env, PRIV_VERSION_1_10_0);
+    env->priv_ver = PRIV_VERSION_1_10_0;
     cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -1211,7 +1206,7 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     if (priv_version >= PRIV_VERSION_1_10_0) {
-        set_priv_version(env, priv_version);
+        env->priv_ver = priv_version;
     }
 
     riscv_cpu_validate_misa_priv(env, &local_err);

[PULL,05/60] target/riscv/cpu.c: remove set_priv_version()

Commit Message

Patch