Message ID | 20230613205857.495165-5-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | target/riscv, KVM: fixes and enhancements | expand |
On Wed, Jun 14, 2023 at 7:01 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Following the same logic used with 'mvendorid' let's also restrict > 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. > > Note that we're getting rid of the default RISCV_CPU_MARCHID value. The > reason is that this is not a good default since it's dynamic, changing > with with every QEMU version, regardless of whether the actual > implementation of the CPU changed from one QEMU version to the other. > Named CPU should set it to a meaningful value instead and generic CPUs > can set whatever they want. > > This is the error thrown for an invalid 'mimpid' value for the veyron-v1 > CPU: > > $ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=2 > qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=2: > Unable to change veyron-v1-riscv-cpu mimpid (0x111) > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++-- > 1 file changed, 32 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6a9a6d34eb..39c550682a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -42,7 +42,6 @@ > #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ > (QEMU_VERSION_MINOR << 8) | \ > (QEMU_VERSION_MICRO)) > -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID > > static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > > @@ -1735,7 +1734,6 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), > - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), > > #ifndef CONFIG_USER_ONLY > DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), > @@ -1854,6 +1852,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, > visit_type_bool(v, name, &value, errp); > } > > +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); > + RISCVCPU *cpu = RISCV_CPU(obj); > + uint64_t prev_val = cpu->cfg.mimpid; > + uint64_t value; > + > + if (!visit_type_uint64(v, name, &value, errp)) { > + return; > + } > + > + if (!dynamic_cpu && prev_val != value) { > + error_setg(errp, "Unable to change %s mimpid (0x%lx)", > + object_get_typename(obj), prev_val); > + return; > + } > + > + cpu->cfg.mimpid = value; > +} > + > +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + bool value = RISCV_CPU(obj)->cfg.mimpid; > + > + visit_type_bool(v, name, &value, errp); > +} > + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -1888,6 +1915,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, > cpu_set_mvendorid, NULL, NULL); > > + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, > + cpu_set_mimpid, NULL, NULL); > + > device_class_set_props(dc, riscv_cpu_properties); > } > > -- > 2.40.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a9a6d34eb..39c550682a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,6 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; @@ -1735,7 +1734,6 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -1854,6 +1852,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, visit_type_bool(v, name, &value, errp); } +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu = RISCV_CPU(obj); + uint64_t prev_val = cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val != value) { + error_setg(errp, "Unable to change %s mimpid (0x%lx)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid = value; +} + +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value = RISCV_CPU(obj)->cfg.mimpid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -1888,6 +1915,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, + cpu_set_mimpid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); }