| Message ID | 20230613205857.495165-4-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv, KVM: fixes and enhancements | expand |
On Wed, Jun 14, 2023 at 7:00 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > We're going to change the handling of mvendorid/marchid/mimpid by the > KVM driver. Since these are always present in all CPUs let's put the > same validation for everyone. > > It doesn't make sense to allow 'mvendorid' to be different than it > is already set in named (vendor) CPUs. Generic (dynamic) CPUs can have > any 'mvendorid' they want. > > Change 'mvendorid' to be a class property created via > 'object_class_property_add', instead of using the DEFINE_PROP_UINT32() > macro. This allow us to define a custom setter for it that will verify, > for named CPUs, if mvendorid is different than it is already set by the > CPU. This is the error thrown for the 'veyron-v1' CPU if 'mvendorid' is > set to an invalid value: > > $ qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mvendorid=2 > qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mvendorid=2: > Unable to change veyron-v1-riscv-cpu mvendorid (0x61f) > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- > 1 file changed, 37 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e904018644..6a9a6d34eb 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1734,7 +1734,6 @@ static void riscv_cpu_add_user_properties(Object *obj) > static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), > DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), > DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), > > @@ -1821,6 +1820,40 @@ static const struct TCGCPUOps riscv_tcg_ops = { > #endif /* !CONFIG_USER_ONLY */ > }; > > +static bool riscv_cpu_is_dynamic(Object *cpu_obj) > +{ > + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; > +} > + > +static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); > + RISCVCPU *cpu = RISCV_CPU(obj); > + uint32_t prev_val = cpu->cfg.mvendorid; > + uint32_t value; > + > + if (!visit_type_uint32(v, name, &value, errp)) { > + return; > + } > + > + if (!dynamic_cpu && prev_val != value) { > + error_setg(errp, "Unable to change %s mvendorid (0x%x)", > + object_get_typename(obj), prev_val); > + return; > + } > + > + cpu->cfg.mvendorid = value; > +} > + > +static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + bool value = RISCV_CPU(obj)->cfg.mvendorid; > + > + visit_type_bool(v, name, &value, errp); > +} > + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -1852,6 +1885,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; > cc->tcg_ops = &riscv_tcg_ops; > > + object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, > + cpu_set_mvendorid, NULL, NULL); > + > device_class_set_props(dc, riscv_cpu_properties); > } > > -- > 2.40.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e904018644..6a9a6d34eb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1734,7 +1734,6 @@ static void riscv_cpu_add_user_properties(Object *obj) static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), @@ -1821,6 +1820,40 @@ static const struct TCGCPUOps riscv_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; +static bool riscv_cpu_is_dynamic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; +} + +static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu = riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu = RISCV_CPU(obj); + uint32_t prev_val = cpu->cfg.mvendorid; + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val != value) { + error_setg(errp, "Unable to change %s mvendorid (0x%x)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mvendorid = value; +} + +static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value = RISCV_CPU(obj)->cfg.mvendorid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -1852,6 +1885,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; cc->tcg_ops = &riscv_tcg_ops; + object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, + cpu_set_mvendorid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); }
We're going to change the handling of mvendorid/marchid/mimpid by the KVM driver. Since these are always present in all CPUs let's put the same validation for everyone. It doesn't make sense to allow 'mvendorid' to be different than it is already set in named (vendor) CPUs. Generic (dynamic) CPUs can have any 'mvendorid' they want. Change 'mvendorid' to be a class property created via 'object_class_property_add', instead of using the DEFINE_PROP_UINT32() macro. This allow us to define a custom setter for it that will verify, for named CPUs, if mvendorid is different than it is already set by the CPU. This is the error thrown for the 'veyron-v1' CPU if 'mvendorid' is set to an invalid value: $ qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mvendorid=2 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mvendorid=2: Unable to change veyron-v1-riscv-cpu mvendorid (0x61f) Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> --- target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-)