[PULL,70/89] target/riscv: Introduce mmuidx_2stage

Message ID	20230505010241.21812-71-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 70/89] target/riscv: Introduce mmuidx_2stage Date: Fri, 5 May 2023 11:02:22 +1000 Message-Id: <20230505010241.21812-71-alistair.francis@wdc.com> In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig \| expand [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig [PULL,02/89] target/riscv: Fix priv version dependency for vector and zfh [PULL,03/89] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,04/89] target/riscv: Simplify type conversion for CPURISCVState [PULL,05/89] target/riscv: Simplify arguments for riscv_csrrw_check [PULL,06/89] target/riscv: refactor Zicond support [PULL,07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions [PULL,08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry [PULL,09/89] target/riscv: add cfg properties for Zc* extension [PULL,10/89] target/riscv: add support for Zca extension [PULL,11/89] target/riscv: add support for Zcf extension [PULL,12/89] target/riscv: add support for Zcd extension [PULL,13/89] target/riscv: add support for Zcb extension [PULL,14/89] target/riscv: add support for Zcmp extension [PULL,15/89] target/riscv: add support for Zcmt extension [PULL,16/89] target/riscv: expose properties for Zc* extension [PULL,17/89] disas/riscv.c: add disasm support for Zc* [PULL,18/89] target/riscv: Add support for Zce [PULL,19/89] target/riscv: Fix itrigger when icount is used [PULL,20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled [PULL,21/89] target/riscv: Remove redundant check on RVH [PULL,22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled [PULL,23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled [PULL,24/89] target/riscv: Convert env->virt to a bool env->virt_enabled [PULL,25/89] target/riscv: Remove redundant parentheses [PULL,26/89] target/riscv: Fix addr type for get_physical_address [PULL,27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault [PULL,28/89] target/riscv: Remove riscv_cpu_virt_enabled() [PULL,29/89] target/riscv: Fix format for indentation [PULL,30/89] target/riscv: Fix format for comments [PULL,31/89] target/riscv: Fix lines with over 80 characters [PULL,32/89] hw/riscv: Add signature dump function for spike to run ACT tests [PULL,33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() [PULL,34/89] target/riscv: remove MISA properties from isa_edata_arr[] [PULL,35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data [PULL,36/89] target/riscv: introduce riscv_cpu_add_misa_properties() [PULL,37/89] target/riscv: remove cpu->cfg.ext_a [PULL,38/89] target/riscv: remove cpu->cfg.ext_c [PULL,39/89] target/riscv: remove cpu->cfg.ext_d [PULL,40/89] target/riscv: remove cpu->cfg.ext_f [PULL,41/89] target/riscv: remove cpu->cfg.ext_i [PULL,42/89] target/riscv: remove cpu->cfg.ext_e [PULL,43/89] target/riscv: remove cpu->cfg.ext_m [PULL,44/89] target/riscv: remove cpu->cfg.ext_s [PULL,45/89] target/riscv: remove cpu->cfg.ext_u [PULL,46/89] target/riscv: remove cpu->cfg.ext_h [PULL,47/89] target/riscv: remove cpu->cfg.ext_j [PULL,48/89] target/riscv: remove cpu->cfg.ext_v [PULL,49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() [PULL,50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() [PULL,51/89] target/riscv: add RVG and remove cpu->cfg.ext_g [PULL,52/89] target/riscv/cpu.c: redesign register_cpu_props() [PULL,53/89] target/riscv: Fix the mstatus.MPP value after executing MRET [PULL,54/89] target/riscv: Use PRV_RESERVED instead of PRV_H [PULL,55/89] target/riscv: Legalize MPP value in write_mstatus [PULL,56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx [PULL,57/89] target/riscv: fix H extension TVM trap [PULL,58/89] target/riscv: Extract virt enabled state from tb flags [PULL,59/89] target/riscv: Add a general status enum for extensions [PULL,60/89] target/riscv: Encode the FS and VS on a normal way for tb flags [PULL,61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags [PULL,62/89] target/riscv: Add a tb flags field for vstart [PULL,63/89] target/riscv: Separate priv from mmu_idx [PULL,64/89] target/riscv: Reduce overhead of MSTATUS_SUM change [PULL,65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX [PULL,66/89] target/riscv: Handle HLV, HSV via helpers [PULL,67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT [PULL,68/89] target/riscv: Introduce mmuidx_sum [PULL,69/89] target/riscv: Introduce mmuidx_priv [PULL,70/89] target/riscv: Introduce mmuidx_2stage [PULL,71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv [PULL,72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index [PULL,73/89] target/riscv: Check SUM in the correct register [PULL,74/89] target/riscv: Hoist second stage mode change to callers [PULL,75/89] target/riscv: Hoist pbmte and hade out of the level loop [PULL,76/89] target/riscv: Move leaf pte processing out of level loop [PULL,77/89] target/riscv: Suppress pte update with is_debug [PULL,78/89] target/riscv: Don't modify SUM with is_debug [PULL,79/89] target/riscv: Merge checks for reserved pte flags [PULL,80/89] target/riscv: Reorg access check in get_physical_address [PULL,81/89] target/riscv: Reorg sum check in get_physical_address [PULL,82/89] hw/intc/riscv_aplic: Zero init APLIC internal state [PULL,83/89] target/riscv: add CPU QOM header [PULL,84/89] target/riscv: add query-cpy-definitions support [PULL,85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU [PULL,86/89] target/riscv: Restore the predicate() NULL check behavior [PULL,87/89] target/riscv: Fix Guest Physical Address Translation [PULL,88/89] riscv: Make sure an exception is raised if a pte is malformed [PULL,89/89] target/riscv: add Ventana's Veyron V1 CPU

Message ID

20230505010241.21812-71-alistair.francis@wdc.com

State

New

Headers

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>,
 Alistair Francis <alistair.francis@wdc.com>,
 Weiwei Li <liweiwei@iscas.ac.cn>,
 Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 70/89] target/riscv: Introduce mmuidx_2stage
Date: Fri,  5 May 2023 11:02:22 +1000
Message-Id: <20230505010241.21812-71-alistair.francis@wdc.com>
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Series

[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig | expand

Commit Message

Alistair Francis May 5, 2023, 1:02 a.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  1 -
 target/riscv/internals.h  |  5 +++++
 target/riscv/cpu_helper.c | 20 ++++++--------------
 3 files changed, 11 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 35cf2e2691..d1f888a790 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -581,7 +581,6 @@  target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
 bool riscv_cpu_vector_enabled(CPURISCVState *env);
 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-bool riscv_cpu_two_stage_lookup(int mmu_idx);
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 G_NORETURN void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
                                                MMUAccessType access_type,
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 4aa1cb409f..b5f823c7ec 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -51,6 +51,11 @@  static inline bool mmuidx_sum(int mmu_idx)
     return (mmu_idx & 3) == MMUIdx_S_SUM;
 }
 
+static inline bool mmuidx_2stage(int mmu_idx)
+{
+    return mmu_idx & MMU_2STAGE_BIT;
+}
+
 /* share data between vector helpers and decode code */
 FIELD(VDATA, VM, 0, 1)
 FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57bb19c76e..9dfd1d739b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -591,11 +591,6 @@  void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
     }
 }
 
-bool riscv_cpu_two_stage_lookup(int mmu_idx)
-{
-    return mmu_idx & MMU_2STAGE_BIT;
-}
-
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
 {
     CPURISCVState *env = &cpu->env;
@@ -779,7 +774,7 @@  static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      * MPRV does not affect the virtual-machine load/store
      * instructions, HLV, HLVX, and HSV.
      */
-    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+    if (mmuidx_2stage(mmu_idx)) {
         mode = get_field(env->hstatus, HSTATUS_SPVP);
     }
 
@@ -1175,8 +1170,7 @@  void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     }
 
     env->badaddr = addr;
-    env->two_stage_lookup = env->virt_enabled ||
-                            riscv_cpu_two_stage_lookup(mmu_idx);
+    env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
     env->two_stage_indirect_lookup = false;
     cpu_loop_exit_restore(cs, retaddr);
 }
@@ -1201,8 +1195,7 @@  void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
         g_assert_not_reached();
     }
     env->badaddr = addr;
-    env->two_stage_lookup = env->virt_enabled ||
-                            riscv_cpu_two_stage_lookup(mmu_idx);
+    env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx);
     env->two_stage_indirect_lookup = false;
     cpu_loop_exit_restore(cs, retaddr);
 }
@@ -1256,7 +1249,7 @@  bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      * MPRV does not affect the virtual-machine load/store
      * instructions, HLV, HLVX, and HSV.
      */
-    if (riscv_cpu_two_stage_lookup(mmu_idx)) {
+    if (mmuidx_2stage(mmu_idx)) {
         mode = get_field(env->hstatus, HSTATUS_SPVP);
     } else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
                get_field(env->mstatus, MSTATUS_MPRV)) {
@@ -1268,7 +1261,7 @@  bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
     pmu_tlb_fill_incr_ctr(cpu, access_type);
     if (env->virt_enabled ||
-        ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
+        ((mmuidx_2stage(mmu_idx) || two_stage_lookup) &&
          access_type != MMU_INST_FETCH)) {
         /* Two stage lookup */
         ret = get_physical_address(env, &pa, &prot, address,
@@ -1366,8 +1359,7 @@  bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     } else {
         raise_mmu_exception(env, address, access_type, pmp_violation,
                             first_stage_error,
-                            env->virt_enabled ||
-                                riscv_cpu_two_stage_lookup(mmu_idx),
+                            env->virt_enabled || mmuidx_2stage(mmu_idx),
                             two_stage_indirect_error);
         cpu_loop_exit_restore(cs, retaddr);
     }

[PULL,70/89] target/riscv: Introduce mmuidx_2stage

Commit Message

Patch