[PULL,66/89] target/riscv: Handle HLV, HSV via helpers

Message ID	20230505010241.21812-67-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Date: Fri, 5 May 2023 11:02:18 +1000 Message-Id: <20230505010241.21812-67-alistair.francis@wdc.com> In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig \| expand [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig [PULL,02/89] target/riscv: Fix priv version dependency for vector and zfh [PULL,03/89] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,04/89] target/riscv: Simplify type conversion for CPURISCVState [PULL,05/89] target/riscv: Simplify arguments for riscv_csrrw_check [PULL,06/89] target/riscv: refactor Zicond support [PULL,07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions [PULL,08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry [PULL,09/89] target/riscv: add cfg properties for Zc* extension [PULL,10/89] target/riscv: add support for Zca extension [PULL,11/89] target/riscv: add support for Zcf extension [PULL,12/89] target/riscv: add support for Zcd extension [PULL,13/89] target/riscv: add support for Zcb extension [PULL,14/89] target/riscv: add support for Zcmp extension [PULL,15/89] target/riscv: add support for Zcmt extension [PULL,16/89] target/riscv: expose properties for Zc* extension [PULL,17/89] disas/riscv.c: add disasm support for Zc* [PULL,18/89] target/riscv: Add support for Zce [PULL,19/89] target/riscv: Fix itrigger when icount is used [PULL,20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled [PULL,21/89] target/riscv: Remove redundant check on RVH [PULL,22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled [PULL,23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled [PULL,24/89] target/riscv: Convert env->virt to a bool env->virt_enabled [PULL,25/89] target/riscv: Remove redundant parentheses [PULL,26/89] target/riscv: Fix addr type for get_physical_address [PULL,27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault [PULL,28/89] target/riscv: Remove riscv_cpu_virt_enabled() [PULL,29/89] target/riscv: Fix format for indentation [PULL,30/89] target/riscv: Fix format for comments [PULL,31/89] target/riscv: Fix lines with over 80 characters [PULL,32/89] hw/riscv: Add signature dump function for spike to run ACT tests [PULL,33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() [PULL,34/89] target/riscv: remove MISA properties from isa_edata_arr[] [PULL,35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data [PULL,36/89] target/riscv: introduce riscv_cpu_add_misa_properties() [PULL,37/89] target/riscv: remove cpu->cfg.ext_a [PULL,38/89] target/riscv: remove cpu->cfg.ext_c [PULL,39/89] target/riscv: remove cpu->cfg.ext_d [PULL,40/89] target/riscv: remove cpu->cfg.ext_f [PULL,41/89] target/riscv: remove cpu->cfg.ext_i [PULL,42/89] target/riscv: remove cpu->cfg.ext_e [PULL,43/89] target/riscv: remove cpu->cfg.ext_m [PULL,44/89] target/riscv: remove cpu->cfg.ext_s [PULL,45/89] target/riscv: remove cpu->cfg.ext_u [PULL,46/89] target/riscv: remove cpu->cfg.ext_h [PULL,47/89] target/riscv: remove cpu->cfg.ext_j [PULL,48/89] target/riscv: remove cpu->cfg.ext_v [PULL,49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() [PULL,50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() [PULL,51/89] target/riscv: add RVG and remove cpu->cfg.ext_g [PULL,52/89] target/riscv/cpu.c: redesign register_cpu_props() [PULL,53/89] target/riscv: Fix the mstatus.MPP value after executing MRET [PULL,54/89] target/riscv: Use PRV_RESERVED instead of PRV_H [PULL,55/89] target/riscv: Legalize MPP value in write_mstatus [PULL,56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx [PULL,57/89] target/riscv: fix H extension TVM trap [PULL,58/89] target/riscv: Extract virt enabled state from tb flags [PULL,59/89] target/riscv: Add a general status enum for extensions [PULL,60/89] target/riscv: Encode the FS and VS on a normal way for tb flags [PULL,61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags [PULL,62/89] target/riscv: Add a tb flags field for vstart [PULL,63/89] target/riscv: Separate priv from mmu_idx [PULL,64/89] target/riscv: Reduce overhead of MSTATUS_SUM change [PULL,65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX [PULL,66/89] target/riscv: Handle HLV, HSV via helpers [PULL,67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT [PULL,68/89] target/riscv: Introduce mmuidx_sum [PULL,69/89] target/riscv: Introduce mmuidx_priv [PULL,70/89] target/riscv: Introduce mmuidx_2stage [PULL,71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv [PULL,72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index [PULL,73/89] target/riscv: Check SUM in the correct register [PULL,74/89] target/riscv: Hoist second stage mode change to callers [PULL,75/89] target/riscv: Hoist pbmte and hade out of the level loop [PULL,76/89] target/riscv: Move leaf pte processing out of level loop [PULL,77/89] target/riscv: Suppress pte update with is_debug [PULL,78/89] target/riscv: Don't modify SUM with is_debug [PULL,79/89] target/riscv: Merge checks for reserved pte flags [PULL,80/89] target/riscv: Reorg access check in get_physical_address [PULL,81/89] target/riscv: Reorg sum check in get_physical_address [PULL,82/89] hw/intc/riscv_aplic: Zero init APLIC internal state [PULL,83/89] target/riscv: add CPU QOM header [PULL,84/89] target/riscv: add query-cpy-definitions support [PULL,85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU [PULL,86/89] target/riscv: Restore the predicate() NULL check behavior [PULL,87/89] target/riscv: Fix Guest Physical Address Translation [PULL,88/89] riscv: Make sure an exception is raised if a pte is malformed [PULL,89/89] target/riscv: add Ventana's Veyron V1 CPU

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6239c99f4c..35cf2e2691 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -639,8 +639,7 @@ FIELD(TB_FLAGS, LMUL, 7, 3) FIELD(TB_FLAGS, SEW, 10, 3) FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) -/* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ @@ -652,8 +651,7 @@ FIELD(TB_FLAGS, VMA, 21, 1) FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) -FIELD(TB_FLAGS, PRIV, 25, 2) +FIELD(TB_FLAGS, PRIV, 24, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1880e95c50..98e97810fd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -123,8 +123,16 @@ DEF_HELPER_1(itrigger_match, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) -DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl) #endif /* Vector functions */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 174a77706b..abf275d2c6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -102,24 +102,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, fs = get_field(env->mstatus, MSTATUS_FS); vs = get_field(env->mstatus, MSTATUS_VS); - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !env->virt_enabled) || - (env->priv == PRV_U && !env->virt_enabled && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - if (env->virt_enabled) { - flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } + if (env->virt_enabled) { + flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); } + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 49179e7a5a..7f83395370 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,6 +427,91 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } +static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) +{ + if (env->priv == PRV_M) { + /* always allowed */ + } else if (env->virt_enabled) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); + } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); + } + + return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; +} + +target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + + return cpu_ldb_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); + + return cpu_ldw_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); + + return cpu_ldl_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); + + return cpu_ldq_mmu(env, addr, oi, ra); +} + +void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); + + cpu_stw_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); + + cpu_stl_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); + + cpu_stq_mmu(env, addr, val, oi, ra); +} + /* * TODO: These implementations are not quite correct. They perform the * access using execute permission just fine, but the final PMP check @@ -434,20 +519,22 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx * which would imply that exact check in tlb_fill. */ -target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr) { - int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, true, ra); MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); - return cpu_ldw_code_mmu(env, address, oi, GETPC()); + return cpu_ldw_code_mmu(env, addr, oi, GETPC()); } -target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr) { - int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, true, ra); MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); - return cpu_ldl_code_mmu(env, address, oi, GETPC()); + return cpu_ldl_code_mmu(env, addr, oi, ra); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6d59348f0c..928da0d3f0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -80,7 +80,6 @@ typedef struct DisasContext { bool virt_inst_excp; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool hlsx; /* vector extension */ bool vill; /* @@ -1163,7 +1162,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->cfg_ptr = &(cpu->cfg); - ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index ae98b45e5e..3e9322130f 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,158 +16,131 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef CONFIG_USER_ONLY -static bool check_access(DisasContext *ctx) -{ - if (!ctx->hlsx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, - offsetof(CPURISCVState, bins)); - if (ctx->virt_enabled) { - generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); - } else { - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); - } - return false; - } +#ifdef CONFIG_USER_ONLY +#define do_hlv(ctx, a, func) false +#define do_hsv(ctx, a, func) false +#else +static void gen_helper_hyp_hlv_b(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_bu(r, e, a); + tcg_gen_ext8s_tl(r, r); +} + +static void gen_helper_hyp_hlv_h(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_hu(r, e, a); + tcg_gen_ext16s_tl(r, r); +} + +static void gen_helper_hyp_hlv_w(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_wu(r, e, a); + tcg_gen_ext32s_tl(r, r); +} + +static bool do_hlv(DisasContext *ctx, arg_r2 *a, + void (*func)(TCGv, TCGv_env, TCGv)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); + + decode_save_opc(ctx); + func(dest, cpu_env, addr); + gen_set_gpr(ctx, a->rd, dest); return true; } -#endif -static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) +static bool do_hsv(DisasContext *ctx, arg_r2_s *a, + void (*func)(TCGv_env, TCGv, TCGv)) { -#ifdef CONFIG_USER_ONLY - return false; -#else + TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); + decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest = dest_gpr(ctx, a->rd); - TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); - int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); - gen_set_gpr(ctx, a->rd, dest); - } + func(cpu_env, addr, data); return true; -#endif } +#endif /* CONFIG_USER_ONLY */ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_SB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_b); } static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESW); + return do_hlv(ctx, a, gen_helper_hyp_hlv_h); } static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_w); } static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_UB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_bu); } static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUW); -} - -static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) -{ -#ifdef CONFIG_USER_ONLY - return false; -#else - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); - TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); - int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); - } - return true; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlv_hu); } static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_SB); + return do_hsv(ctx, a, gen_helper_hyp_hsv_b); } static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESW); + return do_hsv(ctx, a, gen_helper_hyp_hsv_h); } static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESL); + return do_hsv(ctx, a, gen_helper_hyp_hsv_w); } static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_wu); } static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUQ); + return do_hlv(ctx, a, gen_helper_hyp_hlv_d); } static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TEUQ); -} - -#ifndef CONFIG_USER_ONLY -static bool do_hlvx(DisasContext *ctx, arg_r2 *a, - void (*func)(TCGv, TCGv_env, TCGv)) -{ - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest = dest_gpr(ctx, a->rd); - TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); - func(dest, cpu_env, addr); - gen_set_gpr(ctx, a->rd, dest); - } - return true; + return do_hsv(ctx, a, gen_helper_hyp_hsv_d); } -#endif static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_hu); } static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_wu); } static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)

[PULL,66/89] target/riscv: Handle HLV, HSV via helpers

Commit Message

Patch