[PULL,28/89] target/riscv: Remove riscv_cpu_virt_enabled()

Message ID	20230505010241.21812-29-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>, LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, Junqiang Wang <wangjunqiang@iscas.ac.cn>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Date: Fri, 5 May 2023 11:01:40 +1000 Message-Id: <20230505010241.21812-29-alistair.francis@wdc.com> In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig \| expand [PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig [PULL,02/89] target/riscv: Fix priv version dependency for vector and zfh [PULL,03/89] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,04/89] target/riscv: Simplify type conversion for CPURISCVState [PULL,05/89] target/riscv: Simplify arguments for riscv_csrrw_check [PULL,06/89] target/riscv: refactor Zicond support [PULL,07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions [PULL,08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry [PULL,09/89] target/riscv: add cfg properties for Zc* extension [PULL,10/89] target/riscv: add support for Zca extension [PULL,11/89] target/riscv: add support for Zcf extension [PULL,12/89] target/riscv: add support for Zcd extension [PULL,13/89] target/riscv: add support for Zcb extension [PULL,14/89] target/riscv: add support for Zcmp extension [PULL,15/89] target/riscv: add support for Zcmt extension [PULL,16/89] target/riscv: expose properties for Zc* extension [PULL,17/89] disas/riscv.c: add disasm support for Zc* [PULL,18/89] target/riscv: Add support for Zce [PULL,19/89] target/riscv: Fix itrigger when icount is used [PULL,20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled [PULL,21/89] target/riscv: Remove redundant check on RVH [PULL,22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled [PULL,23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled [PULL,24/89] target/riscv: Convert env->virt to a bool env->virt_enabled [PULL,25/89] target/riscv: Remove redundant parentheses [PULL,26/89] target/riscv: Fix addr type for get_physical_address [PULL,27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault [PULL,28/89] target/riscv: Remove riscv_cpu_virt_enabled() [PULL,29/89] target/riscv: Fix format for indentation [PULL,30/89] target/riscv: Fix format for comments [PULL,31/89] target/riscv: Fix lines with over 80 characters [PULL,32/89] hw/riscv: Add signature dump function for spike to run ACT tests [PULL,33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() [PULL,34/89] target/riscv: remove MISA properties from isa_edata_arr[] [PULL,35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data [PULL,36/89] target/riscv: introduce riscv_cpu_add_misa_properties() [PULL,37/89] target/riscv: remove cpu->cfg.ext_a [PULL,38/89] target/riscv: remove cpu->cfg.ext_c [PULL,39/89] target/riscv: remove cpu->cfg.ext_d [PULL,40/89] target/riscv: remove cpu->cfg.ext_f [PULL,41/89] target/riscv: remove cpu->cfg.ext_i [PULL,42/89] target/riscv: remove cpu->cfg.ext_e [PULL,43/89] target/riscv: remove cpu->cfg.ext_m [PULL,44/89] target/riscv: remove cpu->cfg.ext_s [PULL,45/89] target/riscv: remove cpu->cfg.ext_u [PULL,46/89] target/riscv: remove cpu->cfg.ext_h [PULL,47/89] target/riscv: remove cpu->cfg.ext_j [PULL,48/89] target/riscv: remove cpu->cfg.ext_v [PULL,49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() [PULL,50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() [PULL,51/89] target/riscv: add RVG and remove cpu->cfg.ext_g [PULL,52/89] target/riscv/cpu.c: redesign register_cpu_props() [PULL,53/89] target/riscv: Fix the mstatus.MPP value after executing MRET [PULL,54/89] target/riscv: Use PRV_RESERVED instead of PRV_H [PULL,55/89] target/riscv: Legalize MPP value in write_mstatus [PULL,56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx [PULL,57/89] target/riscv: fix H extension TVM trap [PULL,58/89] target/riscv: Extract virt enabled state from tb flags [PULL,59/89] target/riscv: Add a general status enum for extensions [PULL,60/89] target/riscv: Encode the FS and VS on a normal way for tb flags [PULL,61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags [PULL,62/89] target/riscv: Add a tb flags field for vstart [PULL,63/89] target/riscv: Separate priv from mmu_idx [PULL,64/89] target/riscv: Reduce overhead of MSTATUS_SUM change [PULL,65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX [PULL,66/89] target/riscv: Handle HLV, HSV via helpers [PULL,67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT [PULL,68/89] target/riscv: Introduce mmuidx_sum [PULL,69/89] target/riscv: Introduce mmuidx_priv [PULL,70/89] target/riscv: Introduce mmuidx_2stage [PULL,71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv [PULL,72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index [PULL,73/89] target/riscv: Check SUM in the correct register [PULL,74/89] target/riscv: Hoist second stage mode change to callers [PULL,75/89] target/riscv: Hoist pbmte and hade out of the level loop [PULL,76/89] target/riscv: Move leaf pte processing out of level loop [PULL,77/89] target/riscv: Suppress pte update with is_debug [PULL,78/89] target/riscv: Don't modify SUM with is_debug [PULL,79/89] target/riscv: Merge checks for reserved pte flags [PULL,80/89] target/riscv: Reorg access check in get_physical_address [PULL,81/89] target/riscv: Reorg sum check in get_physical_address [PULL,82/89] hw/intc/riscv_aplic: Zero init APLIC internal state [PULL,83/89] target/riscv: add CPU QOM header [PULL,84/89] target/riscv: add query-cpy-definitions support [PULL,85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU [PULL,86/89] target/riscv: Restore the predicate() NULL check behavior [PULL,87/89] target/riscv: Fix Guest Physical Address Translation [PULL,88/89] riscv: Make sure an exception is raised if a pte is malformed [PULL,89/89] target/riscv: add Ventana's Veyron V1 CPU

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ff6b3c6720..995192757a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -585,7 +585,6 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); -bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd9e7bdce6..c304deabd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,7 +556,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); + qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); } #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b0e094a933..fbcdec3c06 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -93,8 +93,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, if (riscv_has_ext(env, RVH)) { if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && + (env->priv == PRV_S && !env->virt_enabled) || + (env->priv == PRV_U && !env->virt_enabled && get_field(env->hstatus, HSTATUS_HU))) { flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } @@ -391,7 +391,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) uint64_t irqs, pending, mie, hsie, vsie; /* Determine interrupt enable state of all privilege modes */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { mie = 1; hsie = 1; vsie = (env->priv < PRV_S) || @@ -452,7 +452,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) bool riscv_cpu_fp_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_FS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { return false; } return true; @@ -465,7 +465,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) bool riscv_cpu_vector_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_VS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { return false; } return true; @@ -483,7 +483,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) if (riscv_has_ext(env, RVF)) { mstatus_mask |= MSTATUS_FS; } - bool current_virt = riscv_cpu_virt_enabled(env); + bool current_virt = env->virt_enabled; g_assert(riscv_has_ext(env, RVH)); @@ -558,11 +558,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) env->geilen = geilen; } -bool riscv_cpu_virt_enabled(CPURISCVState *env) -{ - return env->virt_enabled; -} - /* This function can only be called to set virt when RVH is enabled */ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) { @@ -609,7 +604,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, CPUState *cs = env_cpu(env); uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { gein = get_field(env->hstatus, HSTATUS_VGEIN); vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } @@ -768,7 +763,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (!riscv_cpu_virt_enabled(env) && two_stage) { + if (!env->virt_enabled && two_stage) { use_background = true; } @@ -931,7 +926,7 @@ restart: bool pbmte = env->menvcfg & MENVCFG_PBMTE; bool hade = env->menvcfg & MENVCFG_HADE; - if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { + if (first_stage && two_stage && env->virt_enabled) { pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); hade = hade && (env->henvcfg & HENVCFG_HADE); } @@ -1091,7 +1086,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, switch (access_type) { case MMU_INST_FETCH: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if (env->virt_enabled && !first_stage) { cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { cs->exception_index = page_fault_exceptions ? @@ -1131,11 +1126,11 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int mmu_idx = cpu_mmu_index(&cpu->env, false); if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, - true, riscv_cpu_virt_enabled(env), true)) { + true, env->virt_enabled, true)) { return -1; } - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 0, mmu_idx, false, true, true)) { return -1; @@ -1163,7 +1158,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, } env->badaddr = addr; - env->two_stage_lookup = riscv_cpu_virt_enabled(env) || + env->two_stage_lookup = env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); @@ -1189,7 +1184,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, g_assert_not_reached(); } env->badaddr = addr; - env->two_stage_lookup = riscv_cpu_virt_enabled(env) || + env->two_stage_lookup = env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); @@ -1253,7 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } pmu_tlb_fill_incr_ctr(cpu, access_type); - if (riscv_cpu_virt_enabled(env) || + if (env->virt_enabled || ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && access_type != MMU_INST_FETCH)) { /* Two stage lookup */ @@ -1351,7 +1346,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else { raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, - riscv_cpu_virt_enabled(env) || + env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx), two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); @@ -1658,9 +1653,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (env->priv == PRV_M) { cause = RISCV_EXCP_M_ECALL; - } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { + } else if (env->priv == PRV_S && env->virt_enabled) { cause = RISCV_EXCP_VS_ECALL; - } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) { + } else if (env->priv == PRV_S && !env->virt_enabled) { cause = RISCV_EXCP_S_ECALL; } else if (env->priv == PRV_U) { cause = RISCV_EXCP_U_ECALL; @@ -1683,7 +1678,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { uint64_t hdeleg = async ? env->hideleg : env->hedeleg; - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { + if (env->virt_enabled && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode interrupt @@ -1694,7 +1689,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause = cause - 1; } write_gva = false; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, @@ -1728,12 +1723,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else { /* handle the trap in M-mode */ if (riscv_has_ext(env, RVH)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { riscv_cpu_swap_hypervisor_regs(env); } env->mstatus = set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { + env->virt_enabled); + if (env->virt_enabled && tval) { env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 777d7fbac0..41e56012d5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -45,7 +45,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) #if !defined(CONFIG_USER_ONLY) RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) { - bool virt = riscv_cpu_virt_enabled(env); + bool virt = env->virt_enabled; if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; @@ -135,7 +135,7 @@ skip_ext_pmu_check: return RISCV_EXCP_ILLEGAL_INST; } - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!get_field(env->hcounteren, ctr_mask) || (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -365,7 +365,7 @@ static RISCVException hstateenh(CPURISCVState *env, int csrno) static RISCVException sstateen(CPURISCVState *env, int csrno) { - bool virt = riscv_cpu_virt_enabled(env); + bool virt = env->virt_enabled; int index = csrno - CSR_SSTATEEN0; if (!riscv_cpu_cfg(env)->ext_smstateen) { @@ -430,7 +430,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -536,7 +536,7 @@ static RISCVException seed(CPURISCVState *env, int csrno) */ if (env->priv == PRV_M) { return RISCV_EXCP_NONE; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { if (env->mseccfg & MSECCFG_SSEED) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } else { @@ -964,7 +964,7 @@ static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta = env->virt_enabled ? env->htimedelta : 0; if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -977,7 +977,7 @@ static RISCVException read_time(CPURISCVState *env, int csrno, static RISCVException read_timeh(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta = env->virt_enabled ? env->htimedelta : 0; if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -1031,7 +1031,7 @@ static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, static RISCVException read_stimecmp(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val = env->vstimecmp; } else { *val = env->stimecmp; @@ -1043,7 +1043,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno, static RISCVException read_stimecmph(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val = env->vstimecmp >> 32; } else { *val = env->stimecmp >> 32; @@ -1055,7 +1055,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno, static RISCVException write_stimecmp(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1076,7 +1076,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, static RISCVException write_stimecmph(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1530,7 +1530,7 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) { - if (!riscv_cpu_virt_enabled(env)) { + if (!env->virt_enabled) { return csrno; } @@ -1687,7 +1687,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -1741,7 +1741,7 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -2171,7 +2171,7 @@ static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, static RISCVException read_sstateen(CPURISCVState *env, int csrno, target_ulong *val) { - bool virt = riscv_cpu_virt_enabled(env); + bool virt = env->virt_enabled; int index = csrno - CSR_SSTATEEN0; *val = env->sstateen[index] & env->mstateen[index]; @@ -2185,7 +2185,7 @@ static RISCVException read_sstateen(CPURISCVState *env, int csrno, static RISCVException write_sstateen(CPURISCVState *env, int csrno, uint64_t mask, target_ulong new_val) { - bool virt = riscv_cpu_virt_enabled(env); + bool virt = env->virt_enabled; int index = csrno - CSR_SSTATEEN0; uint64_t wr_mask; uint64_t *reg; @@ -2380,7 +2380,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno, RISCVException ret; uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2590,7 +2590,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno, RISCVException ret; uint64_t mask = env->mideleg & sip_writable_mask; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2783,7 +2783,7 @@ static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) int irq; uint8_t iprio; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return read_vstopi(env, CSR_VSTOPI, val); } @@ -3128,7 +3128,7 @@ static int read_hvipriox(CPURISCVState *env, int first_index, /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } @@ -3154,7 +3154,7 @@ static int write_hvipriox(CPURISCVState *env, int first_index, /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } @@ -3809,7 +3809,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int csr_priv, effective_priv = env->priv; if (riscv_has_ext(env, RVH) && env->priv == PRV_S && - !riscv_cpu_virt_enabled(env)) { + !env->virt_enabled) { /* * We are in HS mode. Add 1 to the effective privledge level to * allow us to access the Hypervisor CSRs. @@ -3819,7 +3819,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, csr_priv = get_field(csrno, 0x300); if (!env->debugger && (effective_priv < csr_priv)) { - if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { + if (csr_priv == (PRV_S + 1) && env->virt_enabled) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index b091293069..1f7aed23c9 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -515,7 +515,7 @@ itrigger_set_count(CPURISCVState *env, int index, int value) static bool check_itrigger_priv(CPURISCVState *env, int index) { target_ulong tdata1 = env->tdata1[index]; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ return (get_field(tdata1, ITRIGGER_VS) == env->priv) || (get_field(tdata1, ITRIGGER_VU) == env->priv); @@ -787,7 +787,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } @@ -806,7 +806,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) pc = env->tdata2[i]; if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ if ((ctrl >> 23) & BIT(env->priv)) { return true; @@ -845,7 +845,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } @@ -880,7 +880,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) } if ((wp->flags & flags) && (wp->vaddr == addr)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ if ((ctrl >> 23) & BIT(env->priv)) { return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eecae9547..c0c4ced7f0 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -140,7 +140,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits, riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - if (riscv_cpu_virt_enabled(env) && + if (env->virt_enabled && (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) || ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); @@ -278,7 +278,7 @@ target_ulong helper_sret(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } - if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTSR)) { + if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); } @@ -293,7 +293,7 @@ target_ulong helper_sret(CPURISCVState *env) } env->mstatus = mstatus; - if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (riscv_has_ext(env, RVH) && !env->virt_enabled) { /* We support Hypervisor extensions and virtulisation is disabled */ target_ulong hstatus = env->hstatus; @@ -365,9 +365,9 @@ void helper_wfi(CPURISCVState *env) bool prv_s = env->priv == PRV_S; if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)) || - (rvs && prv_u && !riscv_cpu_virt_enabled(env))) { + (rvs && prv_u && !env->virt_enabled)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_cpu_virt_enabled(env) && (prv_u || + } else if (env->virt_enabled && (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); } else { @@ -384,7 +384,7 @@ void helper_tlb_flush(CPURISCVState *env) (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + } else if (riscv_has_ext(env, RVH) && env->virt_enabled && get_field(env->hstatus, HSTATUS_VTVM)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); } else { @@ -402,12 +402,12 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); - if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { + if (env->priv == PRV_S && env->virt_enabled) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); } if (env->priv == PRV_M || - (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) { + (env->priv == PRV_S && !env->virt_enabled)) { tlb_flush(cs); return; } @@ -417,7 +417,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) void helper_hyp_gvma_tlb_flush(CPURISCVState *env) { - if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && + if (env->priv == PRV_S && !env->virt_enabled && get_field(env->mstatus, MSTATUS_TVM)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 96ce2dbe49..48ad60be2b 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -109,7 +109,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) CPURISCVState *env = &cpu->env; target_ulong max_val = UINT32_MAX; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; - bool virt_on = riscv_cpu_virt_enabled(env); + bool virt_on = env->virt_enabled; /* Privilege mode filtering */ if ((env->priv == PRV_M && @@ -150,7 +150,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) CPURISCVState *env = &cpu->env; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; uint64_t max_val = UINT64_MAX; - bool virt_on = riscv_cpu_virt_enabled(env); + bool virt_on = env->virt_enabled; /* Privilege mode filtering */ if ((env->priv == PRV_M && diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5dddac44bc..03748f72e6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1169,7 +1169,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->priv_ver = env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - ctx->virt_enabled = riscv_cpu_virt_enabled(env); + ctx->virt_enabled = env->virt_enabled; } else { ctx->virt_enabled = false; }

[PULL,28/89] target/riscv: Remove riscv_cpu_virt_enabled()

Commit Message

Patch