diff mbox series

[v2,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions

Message ID 20230121023542.1726168-2-philipp.tomsich@vrull.eu
State New
Headers show
Series [v2,1/2] target/riscv: add Zicond as an experimental extension | expand

Commit Message

Philipp Tomsich Jan. 21, 2023, 2:35 a.m. UTC
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.

Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.

Also updating MAINTAINERS as trans_xventanacondops.c.inc will not see
active maintenance from here forward.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

Changes in v2:
- Calls into the gen_czero_{eqz,nez} helpers instead of calling
  trans_czero_{eqz,nez} to bypass the require-check and ensure that
  XVentanaCondOps can be enabled/disabled independently of Zicond.

 MAINTAINERS                                    |  2 +-
 .../insn_trans/trans_xventanacondops.c.inc     | 18 +++---------------
 2 files changed, 4 insertions(+), 16 deletions(-)

Comments

Alistair Francis Jan. 23, 2023, 1:28 a.m. UTC | #1
On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> The Zicond standard extension implements the same instruction
> semantics as XVentanaCondOps, although using different mnemonics and
> opcodes.
>
> Point XVentanaCondOps to the (newly implemented) Zicond implementation
> to reduce the future maintenance burden.
>
> Also updating MAINTAINERS as trans_xventanacondops.c.inc will not see
> active maintenance from here forward.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> Changes in v2:
> - Calls into the gen_czero_{eqz,nez} helpers instead of calling
>   trans_czero_{eqz,nez} to bypass the require-check and ensure that
>   XVentanaCondOps can be enabled/disabled independently of Zicond.
>
>  MAINTAINERS                                    |  2 +-
>  .../insn_trans/trans_xventanacondops.c.inc     | 18 +++---------------
>  2 files changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ca914c42fa..293a9d1c8c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -305,7 +305,7 @@ F: target/riscv/insn_trans/trans_zicond.c.inc
>  RISC-V XVentanaCondOps extension
>  M: Philipp Tomsich <philipp.tomsich@vrull.eu>
>  L: qemu-riscv@nongnu.org
> -S: Supported
> +S: Odd Fixes

Should this extension be deprecated then?

Alistair
Philipp Tomsich Jan. 23, 2023, 1:37 a.m. UTC | #2
On Mon, 23 Jan 2023 at 02:29, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > The Zicond standard extension implements the same instruction
> > semantics as XVentanaCondOps, although using different mnemonics and
> > opcodes.
> >
> > Point XVentanaCondOps to the (newly implemented) Zicond implementation
> > to reduce the future maintenance burden.
> >
> > Also updating MAINTAINERS as trans_xventanacondops.c.inc will not see
> > active maintenance from here forward.
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > ---
> >
> > Changes in v2:
> > - Calls into the gen_czero_{eqz,nez} helpers instead of calling
> >   trans_czero_{eqz,nez} to bypass the require-check and ensure that
> >   XVentanaCondOps can be enabled/disabled independently of Zicond.
> >
> >  MAINTAINERS                                    |  2 +-
> >  .../insn_trans/trans_xventanacondops.c.inc     | 18 +++---------------
> >  2 files changed, 4 insertions(+), 16 deletions(-)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index ca914c42fa..293a9d1c8c 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -305,7 +305,7 @@ F: target/riscv/insn_trans/trans_zicond.c.inc
> >  RISC-V XVentanaCondOps extension
> >  M: Philipp Tomsich <philipp.tomsich@vrull.eu>
> >  L: qemu-riscv@nongnu.org
> > -S: Supported
> > +S: Odd Fixes
>
> Should this extension be deprecated then?

The extension is out in the wild (as the Ventana Veyron V1 core
implements it), so we shouldn't deprecate it.
However, this now is the thinnest possible layer of implementation
(and will pick up any fixes/updates from Zicond).

I felt that downgrading it to "Odd Fixes" was the right way to
indicate this.  Let me know if you would like to handle it
differently.

Philipp.
Alistair Francis Jan. 23, 2023, 11:44 a.m. UTC | #3
On Mon, Jan 23, 2023 at 11:37 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> On Mon, 23 Jan 2023 at 02:29, Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
> > <philipp.tomsich@vrull.eu> wrote:
> > >
> > > The Zicond standard extension implements the same instruction
> > > semantics as XVentanaCondOps, although using different mnemonics and
> > > opcodes.
> > >
> > > Point XVentanaCondOps to the (newly implemented) Zicond implementation
> > > to reduce the future maintenance burden.
> > >
> > > Also updating MAINTAINERS as trans_xventanacondops.c.inc will not see
> > > active maintenance from here forward.
> > >
> > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > > ---
> > >
> > > Changes in v2:
> > > - Calls into the gen_czero_{eqz,nez} helpers instead of calling
> > >   trans_czero_{eqz,nez} to bypass the require-check and ensure that
> > >   XVentanaCondOps can be enabled/disabled independently of Zicond.
> > >
> > >  MAINTAINERS                                    |  2 +-
> > >  .../insn_trans/trans_xventanacondops.c.inc     | 18 +++---------------
> > >  2 files changed, 4 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index ca914c42fa..293a9d1c8c 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -305,7 +305,7 @@ F: target/riscv/insn_trans/trans_zicond.c.inc
> > >  RISC-V XVentanaCondOps extension
> > >  M: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > >  L: qemu-riscv@nongnu.org
> > > -S: Supported
> > > +S: Odd Fixes
> >
> > Should this extension be deprecated then?
>
> The extension is out in the wild (as the Ventana Veyron V1 core
> implements it), so we shouldn't deprecate it.
> However, this now is the thinnest possible layer of implementation
> (and will pick up any fixes/updates from Zicond).
>
> I felt that downgrading it to "Odd Fixes" was the right way to
> indicate this.  Let me know if you would like to handle it
> differently.

It probably makes sense to just leave it as supported then. It's up to
a vendor to support their extensions, so I feel that marking it as
"Off Fixes" is a little strange.

Alistair

>
> Philipp.
diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index ca914c42fa..293a9d1c8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -305,7 +305,7 @@  F: target/riscv/insn_trans/trans_zicond.c.inc
 RISC-V XVentanaCondOps extension
 M: Philipp Tomsich <philipp.tomsich@vrull.eu>
 L: qemu-riscv@nongnu.org
-S: Supported
+S: Odd Fixes
 F: target/riscv/XVentanaCondOps.decode
 F: target/riscv/insn_trans/trans_xventanacondops.c.inc
 
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
index 16849e6d4e..38c15f2825 100644
--- a/target/riscv/insn_trans/trans_xventanacondops.c.inc
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
@@ -1,7 +1,7 @@ 
 /*
  * RISC-V translation routines for the XVentanaCondOps extension.
  *
- * Copyright (c) 2021-2022 VRULL GmbH.
+ * Copyright (c) 2021-2023 VRULL GmbH.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,24 +16,12 @@ 
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
-{
-    TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
-    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-
-    tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
-
-    gen_set_gpr(ctx, a->rd, dest);
-    return true;
-}
-
 static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
 {
-    return gen_vt_condmask(ctx, a, TCG_COND_NE);
+    return gen_logic(ctx, a, gen_czero_eqz);
 }
 
 static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
 {
-    return gen_vt_condmask(ctx, a, TCG_COND_EQ);
+    return gen_logic(ctx, a, gen_czero_nez);
 }