[v2,02/15] RISC-V: Adding XTheadSync ISA extension

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.

The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.

Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use helper to synchronize CPUs and perform TLB flushes
- Change implemenation to follow latest spec update
- Use single decoder for XThead extensions

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 target/riscv/cpu.c                         |  2 +
 target/riscv/cpu.h                         |  1 +
 target/riscv/helper.h                      |  1 +
 target/riscv/insn_trans/trans_xthead.c.inc | 86 ++++++++++++++++++++++
 target/riscv/op_helper.c                   |  6 ++
 target/riscv/translate.c                   |  2 +-
 target/riscv/xthead.decode                 |  9 +++
 7 files changed, 106 insertions(+), 1 deletion(-)

On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This patch adds support for the XTheadSync ISA extension.
> The patch uses the T-Head specific decoder and translation.
>
> The implementation introduces a helper to execute synchronization tasks:
> helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.
>
> Changes in v2:
> - Add ISA_EXT_DATA_ENTRY()
> - Use helper to synchronize CPUs and perform TLB flushes
> - Change implemenation to follow latest spec update
> - Use single decoder for XThead extensions
>
> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c                         |  2 +
>  target/riscv/cpu.h                         |  1 +
>  target/riscv/helper.h                      |  1 +
>  target/riscv/insn_trans/trans_xthead.c.inc | 86 ++++++++++++++++++++++
>  target/riscv/op_helper.c                   |  6 ++
>  target/riscv/translate.c                   |  2 +-
>  target/riscv/xthead.decode                 |  9 +++
>  7 files changed, 106 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a90b82c5c5..a848836d2e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
>      ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
>      ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
> +    ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
>      ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
>  };
>
> @@ -1062,6 +1063,7 @@ static Property riscv_cpu_extensions[] = {
>
>      /* Vendor-specific custom extensions */
>      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
> +    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
>      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
>
>      /* These are experimental so mark with 'x-' */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ad1c19f870..4d3da2acfa 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -466,6 +466,7 @@ struct RISCVCPUConfig {
>
>      /* Vendor-specific custom extensions */
>      bool ext_xtheadcmo;
> +    bool ext_xtheadsync;
>      bool ext_XVentanaCondOps;
>
>      uint8_t pmu_num;
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index a03014fe67..ecfb8c280f 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env)
>  DEF_HELPER_1(mret, tl, env)
>  DEF_HELPER_1(wfi, void, env)
>  DEF_HELPER_1(tlb_flush, void, env)
> +DEF_HELPER_1(tlb_flush_all, void, env)
>  #endif
>
>  /* Hypervisor functions */
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
> index 00e75c7dca..6009d61c81 100644
> --- a/target/riscv/insn_trans/trans_xthead.c.inc
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -22,6 +22,12 @@
>      }                                            \
>  } while (0)
>
> +#define REQUIRE_XTHEADSYNC(ctx) do {             \
> +    if (!ctx->cfg_ptr->ext_xtheadsync) {         \
> +        return false;                            \
> +    }                                            \
> +} while (0)
> +
>  /* XTheadCmo */
>
>  static inline int priv_level(DisasContext *ctx)
> @@ -87,3 +93,83 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU)
>  NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
>  NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
>  NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +
> +/* XTheadSync */
> +
> +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
> +{
> +    (void) a;
> +    REQUIRE_XTHEADSYNC(ctx);
> +
> +#ifndef CONFIG_USER_ONLY
> +    REQUIRE_PRIV_MHS(ctx);
> +    decode_save_opc(ctx);
> +    gen_helper_tlb_flush_all(cpu_env);
> +    return true;
> +#else
> +    return false;
> +#endif
> +}
> +
> +#ifndef CONFIG_USER_ONLY
> +static void gen_th_sync_local(DisasContext *ctx)
> +{
> +    /*
> +     * Emulate out-of-order barriers with pipeline flush
> +     * by exiting the translation block.
> +     */
> +    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> +    tcg_gen_exit_tb(NULL, 0);
> +    ctx->base.is_jmp = DISAS_NORETURN;
> +}
> +#endif
> +
> +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a)
> +{
> +    (void) a;
> +    REQUIRE_XTHEADSYNC(ctx);
> +
> +#ifndef CONFIG_USER_ONLY
> +    REQUIRE_PRIV_MHSU(ctx);
> +
> +    /*
> +     * th.sync is an out-of-order barrier.
> +     */
> +    gen_th_sync_local(ctx);
> +
> +    return true;
> +#else
> +    return false;
> +#endif
> +}
> +
> +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a)
> +{
> +    (void) a;
> +    REQUIRE_XTHEADSYNC(ctx);
> +
> +#ifndef CONFIG_USER_ONLY
> +    REQUIRE_PRIV_MHSU(ctx);
> +
> +    /*
> +     * th.sync.i is th.sync plus pipeline flush.
> +     */
> +    gen_th_sync_local(ctx);
> +
> +    return true;
> +#else
> +    return false;
> +#endif
> +}
> +
> +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a)
> +{
> +    /* This instruction has the same behaviour like th.sync.i. */
> +    return trans_th_sync_i(ctx, a);
> +}
> +
> +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a)
> +{
> +    /* This instruction has the same behaviour like th.sync. */
> +    return trans_th_sync(ctx, a);
> +}
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 09f1f5185d..9e3c3f6bf1 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -260,6 +260,12 @@ void helper_tlb_flush(CPURISCVState *env)
>      }
>  }
>
> +void helper_tlb_flush_all(CPURISCVState *env)
> +{
> +    CPUState *cs = env_cpu(env);
> +    tlb_flush_all_cpus_synced(cs);
> +}
> +
>  void helper_hyp_tlb_flush(CPURISCVState *env)
>  {
>      CPUState *cs = env_cpu(env);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 14d9116975..c40617662a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -127,7 +127,7 @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
>
>  static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
>  {
> -    return ctx->cfg_ptr->ext_xtheadcmo;
> +    return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
>  }
>
>  #define MATERIALISE_EXT_PREDICATE(ext)  \
> diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
> index 30533a66f5..1d86f3a012 100644
> --- a/target/riscv/xthead.decode
> +++ b/target/riscv/xthead.decode
> @@ -10,9 +10,11 @@
>
>  # Fields:
>  %rs1       15:5
> +%rs2       20:5
>
>  # Formats
>  @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
> +@rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
>
>  # XTheadCmo
>  th_dcache_call   0000000 00001 00000 000 00000 0001011
> @@ -36,3 +38,10 @@ th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
>  th_l2cache_call  0000000 10101 00000 000 00000 0001011
>  th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
>  th_l2cache_iall  0000000 10110 00000 000 00000 0001011
> +
> +# XTheadSync
> +th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
> +th_sync          0000000 11000 00000 000 00000 0001011
> +th_sync_i        0000000 11010 00000 000 00000 0001011
> +th_sync_is       0000000 11011 00000 000 00000 0001011
> +th_sync_s        0000000 11001 00000 000 00000 0001011
> --
> 2.38.1
>
>