| Message ID | 20221223180016.2068508-14-christoph.muellner@vrull.eu |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for the T-Head vendor extensions | expand |
On Sat, Dec 24, 2022 at 4:07 AM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > From: Christoph Müllner <christoph.muellner@vrull.eu> > > This patch adds the T-Head C906 to the list of known CPUs. > Selecting this CPUs will automatically enable the available > ISA extensions of the CPUs (incl. vendor extensions). > > Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> > > Changes in v2: > - Drop C910 as it does not differ from C906 > - Set priv version to 1.11 (new fmin/fmax behaviour) This should be below the line Otherwise: Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> > --- > target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 2 ++ > target/riscv/cpu_vendorid.h | 6 ++++++ > 3 files changed, 39 insertions(+) > create mode 100644 target/riscv/cpu_vendorid.h > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a38127365e..d3d8587710 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -279,6 +279,36 @@ static void rv64_sifive_e_cpu_init(Object *obj) > cpu->cfg.mmu = false; > } > > +static void rv64_thead_c906_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_11_0); > + > + cpu->cfg.ext_g = true; > + cpu->cfg.ext_c = true; > + cpu->cfg.ext_u = true; > + cpu->cfg.ext_s = true; > + cpu->cfg.ext_icsr = true; > + cpu->cfg.ext_zfh = true; > + cpu->cfg.mmu = true; > + cpu->cfg.ext_xtheadba = true; > + cpu->cfg.ext_xtheadbb = true; > + cpu->cfg.ext_xtheadbs = true; > + cpu->cfg.ext_xtheadcmo = true; > + cpu->cfg.ext_xtheadcondmov = true; > + cpu->cfg.ext_xtheadfmemidx = true; > + cpu->cfg.ext_xtheadmac = true; > + cpu->cfg.ext_xtheadmemidx = true; > + cpu->cfg.ext_xtheadmempair = true; > + cpu->cfg.ext_xtheadsync = true; > + cpu->cfg.ext_xtheadxmae = true; > + > + cpu->cfg.mvendorid = THEAD_VENDOR_ID; > +} > + > static void rv128_base_cpu_init(Object *obj) > { > if (qemu_tcg_mttcg_enabled()) { > @@ -1311,6 +1341,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), > #endif > }; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 897962f107..28184bbe40 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "cpu_vendorid.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -53,6 +54,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #if defined(TARGET_RISCV32) > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h > new file mode 100644 > index 0000000000..a5aa249bc9 > --- /dev/null > +++ b/target/riscv/cpu_vendorid.h > @@ -0,0 +1,6 @@ > +#ifndef TARGET_RISCV_CPU_VENDORID_H > +#define TARGET_RISCV_CPU_VENDORID_H > + > +#define THEAD_VENDOR_ID 0x5b7 > + > +#endif /* TARGET_RISCV_CPU_VENDORID_H */ > -- > 2.38.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a38127365e..d3d8587710 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -279,6 +279,36 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu = false; } +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g = true; + cpu->cfg.ext_c = true; + cpu->cfg.ext_u = true; + cpu->cfg.ext_s = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.mmu = true; + cpu->cfg.ext_xtheadba = true; + cpu->cfg.ext_xtheadbb = true; + cpu->cfg.ext_xtheadbs = true; + cpu->cfg.ext_xtheadcmo = true; + cpu->cfg.ext_xtheadcondmov = true; + cpu->cfg.ext_xtheadfmemidx = true; + cpu->cfg.ext_xtheadmac = true; + cpu->cfg.ext_xtheadmemidx = true; + cpu->cfg.ext_xtheadmempair = true; + cpu->cfg.ext_xtheadsync = true; + cpu->cfg.ext_xtheadxmae = true; + + cpu->cfg.mvendorid = THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1311,6 +1341,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 897962f107..28184bbe40 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "cpu_vendorid.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -53,6 +54,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */