diff mbox series

[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr

Message ID 20220131110201.2303275-3-philipp.tomsich@vrull.eu
State New
Headers show
Series target/riscv: Add XVentanaCondOps and supporting infrastructure changes | expand

Commit Message

Philipp Tomsich Jan. 31, 2022, 11:01 a.m. UTC 
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.

This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

Changes in v5:
- use the typedef in DisasContext instead of the naked struct
  for RISCVCPUConfig

Changes in v3:
- (new patch) copy pointer to element cfg into DisasContext

 target/riscv/translate.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Alistair Francis Feb. 1, 2022, 2:48 a.m. UTC | #1 
On Mon, Jan 31, 2022 at 9:03 PM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> As the number of extensions is growing, copying them individiually
> into the DisasContext will scale less and less... instead we populate
> a pointer to the RISCVCPUConfig structure in the DisasContext.
>
> This adds an extra indirection when checking for the availability of
> an extension (compared to copying the fields into DisasContext).
> While not a performance problem today, we can always (shallow) copy
> the entire structure into the DisasContext (instead of putting a
> pointer to it) if this is ever deemed necessary.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> Changes in v5:
> - use the typedef in DisasContext instead of the naked struct
>   for RISCVCPUConfig
>
> Changes in v3:
> - (new patch) copy pointer to element cfg into DisasContext
>
>  target/riscv/translate.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f0bbe80875..49e40735ce 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -76,6 +76,7 @@ typedef struct DisasContext {
>      int frm;
>      RISCVMXL ol;
>      bool virt_enabled;
> +    const RISCVCPUConfig *cfg_ptr;
>      bool ext_ifencei;
>      bool ext_zfh;
>      bool ext_zfhmin;
> @@ -908,6 +909,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>  #endif
>      ctx->misa_ext = env->misa_ext;
>      ctx->frm = -1;  /* unknown rounding mode */
> +    ctx->cfg_ptr = &(cpu->cfg);
>      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
>      ctx->ext_zfh = cpu->cfg.ext_zfh;
>      ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
> --
> 2.33.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..49e40735ce 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,6 +76,7 @@  typedef struct DisasContext {
     int frm;
     RISCVMXL ol;
     bool virt_enabled;
+    const RISCVCPUConfig *cfg_ptr;
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
@@ -908,6 +909,7 @@  static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #endif
     ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
+    ctx->cfg_ptr = &(cpu->cfg);
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;