| Message ID | 20220106134020.1628889-1-philipp.tomsich@vrull.eu |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Fix position of 'experimental' comment | expand |
On Thu, Jan 6, 2022 at 10:29 PM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set > them to be enabled by default, the comment about experimental > extensions was kept in place above them. This moves it down a few > lines to only cover experimental extensions. > > References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > > --- > > target/riscv/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc'ing qemu-trivial@ On 6/1/22 14:40, Philipp Tomsich wrote: > When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set > them to be enabled by default, the comment about experimental > extensions was kept in place above them. This moves it down a few > lines to only cover experimental extensions. > > References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > --- > > target/riscv/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..e322e729d2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -640,11 +640,12 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > - /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > + > + /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > /* ePMP 0.9.3 */
On Fri, Jan 7, 2022 at 12:30 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set > them to be enabled by default, the comment about experimental > extensions was kept in place above them. This moves it down a few > lines to only cover experimental extensions. > > References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > target/riscv/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..e322e729d2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -640,11 +640,12 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > - /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > + > + /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > /* ePMP 0.9.3 */ > -- > 2.33.1 > >
On Fri, Jan 7, 2022 at 12:30 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set > them to be enabled by default, the comment about experimental > extensions was kept in place above them. This moves it down a few > lines to only cover experimental extensions. > > References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Thanks! Applied to riscv-to-apply.next Alistair > > --- > > target/riscv/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..e322e729d2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -640,11 +640,12 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > - /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > + > + /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > /* ePMP 0.9.3 */ > -- > 2.33.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..e322e729d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -640,11 +640,12 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set them to be enabled by default, the comment about experimental extensions was kept in place above them. This moves it down a few lines to only cover experimental extensions. References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)