diff mbox series

[02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns

Message ID 20211229023348.12606-3-frank.chang@sifive.com
State New
Headers show
Series Add RISC-V RVV Zve32f and Zve64f extensions | expand

Commit Message

Frank Chang Dec. 29, 2021, 2:33 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Alistair Francis Jan. 17, 2022, 10:21 p.m. UTC | #1 
On Wed, Dec 29, 2021 at 12:36 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> All Zve* extensions support the vector configuration instructions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6c285c958b..5b47729a21 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
>  {
>      TCGv s1, dst;
>
> -    if (!require_rvv(s) || !has_ext(s, RVV)) {
> +    if (!require_rvv(s) ||
> +        !(has_ext(s, RVV) || s->ext_zve64f)) {
>          return false;
>      }
>
> @@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
>  {
>      TCGv dst;
>
> -    if (!require_rvv(s) || !has_ext(s, RVV)) {
> +    if (!require_rvv(s) ||
> +        !(has_ext(s, RVV) || s->ext_zve64f)) {
>          return false;
>      }
>
> --
> 2.31.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c285c958b..5b47729a21 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -129,7 +129,8 @@  static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !has_ext(s, RVV)) {
+    if (!require_rvv(s) ||
+        !(has_ext(s, RVV) || s->ext_zve64f)) {
         return false;
     }
 
@@ -164,7 +165,8 @@  static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !has_ext(s, RVV)) {
+    if (!require_rvv(s) ||
+        !(has_ext(s, RVV) || s->ext_zve64f)) {
         return false;
     }