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[09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns

Message ID 20211229023348.12606-10-frank.chang@sifive.com
State New
Headers show
Series Add RISC-V RVV Zve32f and Zve64f extensions | expand

Commit Message

Frank Chang Dec. 29, 2021, 2:33 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Alistair Francis Jan. 17, 2022, 10:53 p.m. UTC | #1 
On Wed, Dec 29, 2021 at 12:45 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector narrowing conversion instructions are provided to and from all
> supported integer EEWs for Zve64f extension.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9ca8d502b2..230c475d6c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2824,14 +2824,16 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
>  {
>      return opfv_narrow_check(s, a) &&
>             require_rvf(s) &&
> -           (s->sew != MO_64);
> +           (s->sew != MO_64) &&
> +           require_zve64f(s);
>  }
>
>  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
>  {
>      return opfv_narrow_check(s, a) &&
>             require_scale_rvf(s) &&
> -           (s->sew != MO_8);
> +           (s->sew != MO_8) &&
> +           require_scale_zve64f(s);
>  }
>
>  #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
> @@ -2880,7 +2882,8 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
>             require_scale_rvf(s) &&
>             vext_check_isa_ill(s) &&
>             /* OPFV narrowing instructions ignore vs1 check */
> -           vext_check_sd(s, a->rd, a->rs2, a->vm);
> +           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve64f(s);
>  }
>
>  #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \
> --
> 2.31.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9ca8d502b2..230c475d6c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2824,14 +2824,16 @@  static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           (s->sew != MO_64);
+           (s->sew != MO_64) &&
+           require_zve64f(s);
 }
 
 static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           (s->sew != MO_8) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -2880,7 +2882,8 @@  static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV narrowing instructions ignore vs1 check */
-           vext_check_sd(s, a->rd, a->rs2, a->vm);
+           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \