Message ID | 20210829175120.19413-4-space.monkey.delivers@gmail.com |
---|---|
State | New |
Headers | show |
Series | [v10,1/7,RISCV_PM] Add J-extension into RISC-V | expand |
On Mon, Aug 30, 2021 at 3:54 AM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > --- > target/riscv/cpu.c | 6 + > target/riscv/cpu.h | 11 ++ > target/riscv/csr.c | 276 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 293 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 991a6bb760..4178eecbec 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -553,6 +553,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > set_vext_version(env, vext_version); > } > + if (cpu->cfg.ext_j) { > +#ifndef CONFIG_USER_ONLY > + /* mmte is supposed to have pm.current hardwired to 1 */ > + env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); This should probably be in the reset function instead. > +#endif > + } > > set_misa(env, target_misa); > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 451a1637a1..94e680cbd0 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -238,6 +238,17 @@ struct CPURISCVState { > > /* True if in debugger mode. */ > bool debugger; > + > + /* > + * CSRs for PointerMasking extension > + */ > + target_ulong mmte; > + target_ulong mpmmask; > + target_ulong mpmbase; > + target_ulong spmmask; > + target_ulong spmbase; > + target_ulong upmmask; > + target_ulong upmbase; > #endif > > float_status fp_status; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9a4ed18ac5..42a0867e5d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -192,6 +192,16 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) > > } > > +/* Checks if PointerMasking registers could be accessed */ > +static RISCVException pointer_masking(CPURISCVState *env, int csrno) > +{ > + /* Check if j-ext is present */ > + if (riscv_has_ext(env, RVJ)) { > + return RISCV_EXCP_NONE; > + } > + return RISCV_EXCP_ILLEGAL_INST; > +} > + > static RISCVException pmp(CPURISCVState *env, int csrno) > { > if (riscv_feature(env, RISCV_FEATURE_PMP)) { > @@ -1404,6 +1414,259 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > +/* > + * Functions to access Pointer Masking feature registers > + * We have to check if current priv lvl could modify > + * csr in given mode > + */ > +static bool check_pm_current_disabled(CPURISCVState *env, int csrno) > +{ > + int csr_priv = get_field(csrno, 0x300); Can you add a newline between declarations and code? > + /* > + * If priv lvls differ that means we're accessing csr from higher priv lvl, > + * so allow the access > + */ > + if (env->priv != csr_priv) { > + return false; > + } > + int cur_bit_pos; Can you keep all of the declarations at the start of blocks please. > + switch (env->priv) { > + case PRV_M: > + cur_bit_pos = M_PM_CURRENT; > + break; > + case PRV_S: > + cur_bit_pos = S_PM_CURRENT; > + break; > + case PRV_U: > + cur_bit_pos = U_PM_CURRENT; > + break; > + default: > + g_assert_not_reached(); > + } > + int pm_current = get_field(env->mmte, cur_bit_pos); > + /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ > + return !pm_current; > +} > + > +static RISCVException read_mmte(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mmte & MMTE_MASK; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mmte(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + target_ulong wpri_val = val & MMTE_MASK; > + if (val != wpri_val) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", > + val, wpri_val); > + } > + /* for machine mode pm.current is hardwired to 1 */ > + wpri_val |= MMTE_M_PM_CURRENT; > + > + /* hardwiring pm.instruction bit to 0, since it's not supported yet */ > + wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); > + env->mmte = wpri_val | PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_smte(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mmte & SMTE_MASK; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_smte(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + target_ulong wpri_val = val & SMTE_MASK; > + if (val != wpri_val) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", > + val, wpri_val); > + } > + > + /* if pm.current==0 we can't modify current PM CSRs */ > + if (check_pm_current_disabled(env, csrno)) { > + return RISCV_EXCP_NONE; > + } > + > + target_ulong new_val = wpri_val | (env->mmte & ~SMTE_MASK); > + write_mmte(env, csrno, new_val); You don't really need the new_val variable here. > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_umte(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mmte & UMTE_MASK; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_umte(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + target_ulong wpri_val = val & UMTE_MASK; > + if (val != wpri_val) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", > + val, wpri_val); > + } > + > + if (check_pm_current_disabled(env, csrno)) { > + return RISCV_EXCP_NONE; > + } > + > + target_ulong new_val = wpri_val | (env->mmte & ~UMTE_MASK); > + write_mmte(env, csrno, new_val); Same here > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_mpmmask(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mpmmask; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mpmmask(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + env->mpmmask = val; > + env->mmte |= PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_spmmask(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->spmmask; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_spmmask(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + /* if pm.current==0 we can't modify current PM CSRs */ > + if (check_pm_current_disabled(env, csrno)) { > + return RISCV_EXCP_NONE; > + } > + env->spmmask = val; > + env->mmte |= PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_upmmask(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->upmmask; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_upmmask(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + /* if pm.current==0 we can't modify current PM CSRs */ > + if (check_pm_current_disabled(env, csrno)) { > + return RISCV_EXCP_NONE; > + } > + env->upmmask = val; > + env->mmte |= PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_mpmbase(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mpmbase; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mpmbase(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + env->mpmbase = val; > + env->mmte |= PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_spmbase(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->spmbase; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_spmbase(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + /* if pm.current==0 we can't modify current PM CSRs */ > + if (check_pm_current_disabled(env, csrno)) { > + return RISCV_EXCP_NONE; > + } > + env->spmbase = val; > + env->mmte |= PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException read_upmbase(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->upmbase; > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_upmbase(CPURISCVState *env, int csrno, > + target_ulong val) > +{ > + uint64_t mstatus; > + /* if pm.current==0 we can't modify current PM CSRs */ > + if (check_pm_current_disabled(env, csrno)) { > + return RISCV_EXCP_NONE; > + } > + env->upmbase = val; > + env->mmte |= PM_EXT_DIRTY; > + > + /* Set XS and SD bits, since PM CSRs are dirty */ > + mstatus = env->mstatus | MSTATUS_XS; > + write_mstatus(env, csrno, mstatus); > + return RISCV_EXCP_NONE; > +} > + > #endif > > /* > @@ -1636,6 +1899,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, > [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, > > + /* User Pointer Masking */ > + [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, > + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, > + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, > + /* Machine Pointer Masking */ > + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, > + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, > + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, > + /* Supervisor Pointer Masking */ > + [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, > + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, > + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, > + Looks good! Just a few style nits and then this should be good to go. Alistair > /* Performance Counters */ > [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, > [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, > -- > 2.20.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..4178eecbec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -553,6 +553,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_j) { +#ifndef CONFIG_USER_ONLY + /* mmte is supposed to have pm.current hardwired to 1 */ + env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); +#endif + } set_misa(env, target_misa); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 451a1637a1..94e680cbd0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -238,6 +238,17 @@ struct CPURISCVState { /* True if in debugger mode. */ bool debugger; + + /* + * CSRs for PointerMasking extension + */ + target_ulong mmte; + target_ulong mpmmask; + target_ulong mpmbase; + target_ulong spmmask; + target_ulong spmbase; + target_ulong upmmask; + target_ulong upmbase; #endif float_status fp_status; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9a4ed18ac5..42a0867e5d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -192,6 +192,16 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) } +/* Checks if PointerMasking registers could be accessed */ +static RISCVException pointer_masking(CPURISCVState *env, int csrno) +{ + /* Check if j-ext is present */ + if (riscv_has_ext(env, RVJ)) { + return RISCV_EXCP_NONE; + } + return RISCV_EXCP_ILLEGAL_INST; +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_feature(env, RISCV_FEATURE_PMP)) { @@ -1404,6 +1414,259 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +/* + * Functions to access Pointer Masking feature registers + * We have to check if current priv lvl could modify + * csr in given mode + */ +static bool check_pm_current_disabled(CPURISCVState *env, int csrno) +{ + int csr_priv = get_field(csrno, 0x300); + /* + * If priv lvls differ that means we're accessing csr from higher priv lvl, + * so allow the access + */ + if (env->priv != csr_priv) { + return false; + } + int cur_bit_pos; + switch (env->priv) { + case PRV_M: + cur_bit_pos = M_PM_CURRENT; + break; + case PRV_S: + cur_bit_pos = S_PM_CURRENT; + break; + case PRV_U: + cur_bit_pos = U_PM_CURRENT; + break; + default: + g_assert_not_reached(); + } + int pm_current = get_field(env->mmte, cur_bit_pos); + /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ + return !pm_current; +} + +static RISCVException read_mmte(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mmte & MMTE_MASK; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mmte(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + target_ulong wpri_val = val & MMTE_MASK; + if (val != wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", + val, wpri_val); + } + /* for machine mode pm.current is hardwired to 1 */ + wpri_val |= MMTE_M_PM_CURRENT; + + /* hardwiring pm.instruction bit to 0, since it's not supported yet */ + wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); + env->mmte = wpri_val | PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + +static RISCVException read_smte(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mmte & SMTE_MASK; + return RISCV_EXCP_NONE; +} + +static RISCVException write_smte(CPURISCVState *env, int csrno, + target_ulong val) +{ + target_ulong wpri_val = val & SMTE_MASK; + if (val != wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", + val, wpri_val); + } + + /* if pm.current==0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + + target_ulong new_val = wpri_val | (env->mmte & ~SMTE_MASK); + write_mmte(env, csrno, new_val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_umte(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mmte & UMTE_MASK; + return RISCV_EXCP_NONE; +} + +static RISCVException write_umte(CPURISCVState *env, int csrno, + target_ulong val) +{ + target_ulong wpri_val = val & UMTE_MASK; + if (val != wpri_val) { + qemu_log_mask(LOG_GUEST_ERROR, + "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", + val, wpri_val); + } + + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + + target_ulong new_val = wpri_val | (env->mmte & ~UMTE_MASK); + write_mmte(env, csrno, new_val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_mpmmask(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mpmmask; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mpmmask(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + env->mpmmask = val; + env->mmte |= PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + +static RISCVException read_spmmask(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->spmmask; + return RISCV_EXCP_NONE; +} + +static RISCVException write_spmmask(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current==0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->spmmask = val; + env->mmte |= PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + +static RISCVException read_upmmask(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->upmmask; + return RISCV_EXCP_NONE; +} + +static RISCVException write_upmmask(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current==0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->upmmask = val; + env->mmte |= PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + +static RISCVException read_mpmbase(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mpmbase; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mpmbase(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + env->mpmbase = val; + env->mmte |= PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + +static RISCVException read_spmbase(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->spmbase; + return RISCV_EXCP_NONE; +} + +static RISCVException write_spmbase(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current==0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->spmbase = val; + env->mmte |= PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + +static RISCVException read_upmbase(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->upmbase; + return RISCV_EXCP_NONE; +} + +static RISCVException write_upmbase(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mstatus; + /* if pm.current==0 we can't modify current PM CSRs */ + if (check_pm_current_disabled(env, csrno)) { + return RISCV_EXCP_NONE; + } + env->upmbase = val; + env->mmte |= PM_EXT_DIRTY; + + /* Set XS and SD bits, since PM CSRs are dirty */ + mstatus = env->mstatus | MSTATUS_XS; + write_mstatus(env, csrno, mstatus); + return RISCV_EXCP_NONE; +} + #endif /* @@ -1636,6 +1899,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + /* User Pointer Masking */ + [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, + /* Machine Pointer Masking */ + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, + /* Supervisor Pointer Masking */ + [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, + /* Performance Counters */ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> --- target/riscv/cpu.c | 6 + target/riscv/cpu.h | 11 ++ target/riscv/csr.c | 276 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+)