Message ID | 20210825165907.34026-9-philipp.tomsich@vrull.eu |
---|---|
State | New |
Headers | show |
Series | target/riscv: Update QEmu for Zb[abcs] 1.0.0 | expand |
On Thu, Aug 26, 2021 at 3:11 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > This reassigns the instructions that are part of Zbb into it, with the > notable exceptions of the instructions (rev8, zext.w and orc.b) that > changed due to gorci, grevi and pack not being part of Zb[abcs]. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > (no changes since v3) > > Changes in v3: > - The changes to the Zbb instructions (i.e. use the REQUIRE_ZBB macro) > are now in a separate commit. > > target/riscv/insn32.decode | 40 ++++++++++---------- > target/riscv/insn_trans/trans_rvb.c.inc | 50 ++++++++++++++----------- > 2 files changed, 49 insertions(+), 41 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 04711111c8..faa56836d8 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -671,45 +671,47 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r > sh3add_uw 0010000 .......... 110 ..... 0111011 @r > slli_uw 00001 ............ 001 ..... 0011011 @sh > > -# *** RV32B Standard Extension *** > +# *** RV32 Zbb Standard Extension *** > +andn 0100000 .......... 111 ..... 0110011 @r > clz 011000 000000 ..... 001 ..... 0010011 @r2 > -ctz 011000 000001 ..... 001 ..... 0010011 @r2 > cpop 011000 000010 ..... 001 ..... 0010011 @r2 > +ctz 011000 000001 ..... 001 ..... 0010011 @r2 > +max 0000101 .......... 110 ..... 0110011 @r > +maxu 0000101 .......... 111 ..... 0110011 @r > +min 0000101 .......... 100 ..... 0110011 @r > +minu 0000101 .......... 101 ..... 0110011 @r > +orn 0100000 .......... 110 ..... 0110011 @r > +rol 0110000 .......... 001 ..... 0110011 @r > +ror 0110000 .......... 101 ..... 0110011 @r > +rori 01100 ............ 101 ..... 0010011 @sh > sext_b 011000 000100 ..... 001 ..... 0010011 @r2 > sext_h 011000 000101 ..... 001 ..... 0010011 @r2 > - > -andn 0100000 .......... 111 ..... 0110011 @r > -orn 0100000 .......... 110 ..... 0110011 @r > xnor 0100000 .......... 100 ..... 0110011 @r > + > +# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** > +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 > +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 > +rolw 0110000 .......... 001 ..... 0111011 @r > +roriw 0110000 .......... 101 ..... 0011011 @sh5 > +rorw 0110000 .......... 101 ..... 0111011 @r > + > +# *** RV32B Standard Extension *** > pack 0000100 .......... 100 ..... 0110011 @r > packu 0100100 .......... 100 ..... 0110011 @r > packh 0000100 .......... 111 ..... 0110011 @r > -min 0000101 .......... 100 ..... 0110011 @r > -minu 0000101 .......... 101 ..... 0110011 @r > -max 0000101 .......... 110 ..... 0110011 @r > -maxu 0000101 .......... 111 ..... 0110011 @r > -ror 0110000 .......... 101 ..... 0110011 @r > -rol 0110000 .......... 001 ..... 0110011 @r > grev 0110100 .......... 101 ..... 0110011 @r > gorc 0010100 .......... 101 ..... 0110011 @r > > -rori 01100. ........... 101 ..... 0010011 @sh > grevi 01101. ........... 101 ..... 0010011 @sh > gorci 00101. ........... 101 ..... 0010011 @sh > > # *** RV64B Standard Extension (in addition to RV32B) *** > -clzw 0110000 00000 ..... 001 ..... 0011011 @r2 > -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 > -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 > - > packw 0000100 .......... 100 ..... 0111011 @r > packuw 0100100 .......... 100 ..... 0111011 @r > -rorw 0110000 .......... 101 ..... 0111011 @r > -rolw 0110000 .......... 001 ..... 0111011 @r > grevw 0110100 .......... 101 ..... 0111011 @r > gorcw 0010100 .......... 101 ..... 0111011 @r > > -roriw 0110000 .......... 101 ..... 0011011 @sh5 > greviw 0110100 .......... 101 ..... 0011011 @sh5 > gorciw 0010100 .......... 101 ..... 0011011 @sh5 > > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index 6a3e0c6a09..03b3724c96 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -1,5 +1,5 @@ > /* > - * RISC-V translation routines for the Zb[acs] Standard Extension. > + * RISC-V translation routines for the Zb[abcs] Standard Extension. > * > * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com > * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com > @@ -24,6 +24,12 @@ > } \ > } while (0) > > +#define REQUIRE_ZBB(ctx) do { \ > + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_ZBC(ctx) do { \ > if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ > return false; \ > @@ -38,37 +44,37 @@ > > static bool trans_clz(DisasContext *ctx, arg_clz *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, gen_clz); > } > > static bool trans_ctz(DisasContext *ctx, arg_ctz *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, gen_ctz); > } > > static bool trans_cpop(DisasContext *ctx, arg_cpop *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, tcg_gen_ctpop_tl); > } > > static bool trans_andn(DisasContext *ctx, arg_andn *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_andc_tl); > } > > static bool trans_orn(DisasContext *ctx, arg_orn *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_orc_tl); > } > > static bool trans_xnor(DisasContext *ctx, arg_xnor *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_eqv_tl); > } > > @@ -92,37 +98,37 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a) > > static bool trans_min(DisasContext *ctx, arg_min *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_smin_tl); > } > > static bool trans_max(DisasContext *ctx, arg_max *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_smax_tl); > } > > static bool trans_minu(DisasContext *ctx, arg_minu *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_umin_tl); > } > > static bool trans_maxu(DisasContext *ctx, arg_maxu *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_arith(ctx, a, tcg_gen_umax_tl); > } > > static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, tcg_gen_ext8s_tl); > } > > static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, tcg_gen_ext16s_tl); > } > > @@ -176,19 +182,19 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) > > static bool trans_ror(DisasContext *ctx, arg_ror *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_shift(ctx, a, tcg_gen_rotr_tl); > } > > static bool trans_rori(DisasContext *ctx, arg_rori *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_shifti(ctx, a, tcg_gen_rotr_tl); > } > > static bool trans_rol(DisasContext *ctx, arg_rol *a) > { > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_shift(ctx, a, tcg_gen_rotl_tl); > } > > @@ -235,21 +241,21 @@ GEN_TRANS_SHADD(3) > static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > { > REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, gen_clzw); > } > > static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) > { > REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, gen_ctzw); > } > > static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) > { > REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_unary(ctx, a, gen_cpopw); > } > > @@ -270,21 +276,21 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) > static bool trans_rorw(DisasContext *ctx, arg_rorw *a) > { > REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_shiftw(ctx, a, gen_rorw); > } > > static bool trans_roriw(DisasContext *ctx, arg_roriw *a) > { > REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_shiftiw(ctx, a, gen_rorw); > } > > static bool trans_rolw(DisasContext *ctx, arg_rolw *a) > { > REQUIRE_64BIT(ctx); > - REQUIRE_EXT(ctx, RVB); > + REQUIRE_ZBB(ctx); > return gen_shiftw(ctx, a, gen_rolw); > } > > -- > 2.25.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 04711111c8..faa56836d8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -671,45 +671,47 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r sh3add_uw 0010000 .......... 110 ..... 0111011 @r slli_uw 00001 ............ 001 ..... 0011011 @sh -# *** RV32B Standard Extension *** +# *** RV32 Zbb Standard Extension *** +andn 0100000 .......... 111 ..... 0110011 @r clz 011000 000000 ..... 001 ..... 0010011 @r2 -ctz 011000 000001 ..... 001 ..... 0010011 @r2 cpop 011000 000010 ..... 001 ..... 0010011 @r2 +ctz 011000 000001 ..... 001 ..... 0010011 @r2 +max 0000101 .......... 110 ..... 0110011 @r +maxu 0000101 .......... 111 ..... 0110011 @r +min 0000101 .......... 100 ..... 0110011 @r +minu 0000101 .......... 101 ..... 0110011 @r +orn 0100000 .......... 110 ..... 0110011 @r +rol 0110000 .......... 001 ..... 0110011 @r +ror 0110000 .......... 101 ..... 0110011 @r +rori 01100 ............ 101 ..... 0010011 @sh sext_b 011000 000100 ..... 001 ..... 0010011 @r2 sext_h 011000 000101 ..... 001 ..... 0010011 @r2 - -andn 0100000 .......... 111 ..... 0110011 @r -orn 0100000 .......... 110 ..... 0110011 @r xnor 0100000 .......... 100 ..... 0110011 @r + +# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** +clzw 0110000 00000 ..... 001 ..... 0011011 @r2 +ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 +cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 +rolw 0110000 .......... 001 ..... 0111011 @r +roriw 0110000 .......... 101 ..... 0011011 @sh5 +rorw 0110000 .......... 101 ..... 0111011 @r + +# *** RV32B Standard Extension *** pack 0000100 .......... 100 ..... 0110011 @r packu 0100100 .......... 100 ..... 0110011 @r packh 0000100 .......... 111 ..... 0110011 @r -min 0000101 .......... 100 ..... 0110011 @r -minu 0000101 .......... 101 ..... 0110011 @r -max 0000101 .......... 110 ..... 0110011 @r -maxu 0000101 .......... 111 ..... 0110011 @r -ror 0110000 .......... 101 ..... 0110011 @r -rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r -rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh # *** RV64B Standard Extension (in addition to RV32B) *** -clzw 0110000 00000 ..... 001 ..... 0011011 @r2 -ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 -cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 - packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -rorw 0110000 .......... 101 ..... 0111011 @r -rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 6a3e0c6a09..03b3724c96 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zb[acs] Standard Extension. + * RISC-V translation routines for the Zb[abcs] Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com @@ -24,6 +24,12 @@ } \ } while (0) +#define REQUIRE_ZBB(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_ZBC(ctx) do { \ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ return false; \ @@ -38,37 +44,37 @@ static bool trans_clz(DisasContext *ctx, arg_clz *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_clz); } static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_ctz); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, tcg_gen_ctpop_tl); } static bool trans_andn(DisasContext *ctx, arg_andn *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_andc_tl); } static bool trans_orn(DisasContext *ctx, arg_orn *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_orc_tl); } static bool trans_xnor(DisasContext *ctx, arg_xnor *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_eqv_tl); } @@ -92,37 +98,37 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a) static bool trans_min(DisasContext *ctx, arg_min *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_smin_tl); } static bool trans_max(DisasContext *ctx, arg_max *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_smax_tl); } static bool trans_minu(DisasContext *ctx, arg_minu *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_umin_tl); } static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_arith(ctx, a, tcg_gen_umax_tl); } static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, tcg_gen_ext8s_tl); } static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, tcg_gen_ext16s_tl); } @@ -176,19 +182,19 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) static bool trans_ror(DisasContext *ctx, arg_ror *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift(ctx, a, tcg_gen_rotr_tl); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shifti(ctx, a, tcg_gen_rotr_tl); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shift(ctx, a, tcg_gen_rotl_tl); } @@ -235,21 +241,21 @@ GEN_TRANS_SHADD(3) static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_clzw); } static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_ctzw); } static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_unary(ctx, a, gen_cpopw); } @@ -270,21 +276,21 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shiftw(ctx, a, gen_rorw); } static bool trans_roriw(DisasContext *ctx, arg_roriw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shiftiw(ctx, a, gen_rorw); } static bool trans_rolw(DisasContext *ctx, arg_rolw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBB(ctx); return gen_shiftw(ctx, a, gen_rolw); }