Message ID | 20210810014552.4884-1-zhiwei_liu@c-sky.com |
---|---|
State | New |
Headers | show |
Series | [v2,1/1] target/riscv: Add User CSRs read-only check | expand |
On Tue, Aug 10, 2021 at 11:48 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > For U-mode CSRs, read-only check is also needed. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9a4ed18ac5..5499cae94a 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, > RISCVException ret; > target_ulong old_value; > RISCVCPU *cpu = env_archcpu(env); > + int read_only = get_field(csrno, 0xC00) == 3; > > /* check privileges and return -1 if check fails */ > #if !defined(CONFIG_USER_ONLY) > int effective_priv = env->priv; > - int read_only = get_field(csrno, 0xC00) == 3; > > if (riscv_has_ext(env, RVH) && > env->priv == PRV_S && > @@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, > effective_priv++; > } > > - if ((write_mask && read_only) || > - (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { > + if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { > return RISCV_EXCP_ILLEGAL_INST; > } > #endif > + if (write_mask && read_only) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > > /* ensure the CSR extension is enabled. */ > if (!cpu->cfg.ext_icsr) { > -- > 2.17.1 > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9a4ed18ac5..5499cae94a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, RISCVException ret; target_ulong old_value; RISCVCPU *cpu = env_archcpu(env); + int read_only = get_field(csrno, 0xC00) == 3; /* check privileges and return -1 if check fails */ #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; - int read_only = get_field(csrno, 0xC00) == 3; if (riscv_has_ext(env, RVH) && env->priv == PRV_S && @@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, effective_priv++; } - if ((write_mask && read_only) || - (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { + if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { return RISCV_EXCP_ILLEGAL_INST; } #endif + if (write_mask && read_only) { + return RISCV_EXCP_ILLEGAL_INST; + } /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) {