Message ID | 20210110185109.29841-4-space.monkey.delivers@gmail.com |
---|---|
State | New |
Headers | show |
Series | RISC-V Pointer Masking implementation | expand |
On Sun, Jan 10, 2021 at 10:57 AM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d50f09b757..19398977d3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); > } > + if (riscv_has_ext(env, RVJ)) { > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); > + switch (env->priv) { > + case PRV_U: > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", > + env->upmbase); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", > + env->upmmask); > + break; > + case PRV_S: > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", > + env->spmbase); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", > + env->spmmask); > + break; > + case PRV_M: > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", > + env->mpmbase); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", > + env->mpmmask); > + break; > + default: > + g_assert_not_reached(); > + } > + } > #endif > > for (i = 0; i < 32; i++) { > -- > 2.20.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d50f09b757..19398977d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + if (riscv_has_ext(env, RVJ)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); + switch (env->priv) { + case PRV_U: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", + env->upmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", + env->upmmask); + break; + case PRV_S: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", + env->spmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", + env->spmmask); + break; + case PRV_M: + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", + env->mpmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", + env->mpmmask); + break; + default: + g_assert_not_reached(); + } + } #endif for (i = 0; i < 32; i++) {