| Message ID | 20210110185109.29841-2-space.monkey.delivers@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V Pointer Masking implementation | expand |
On Sun, Jan 10, 2021 at 10:51 AM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6339e84819..d152842e37 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -72,6 +72,7 @@ > #define RVS RV('S') > #define RVU RV('U') > #define RVH RV('H') > +#define RVJ RV('J') > > /* S extension denotes that Supervisor mode exists, however it is possible > to have a core that support S mode but does not have an MMU and there > @@ -285,6 +286,7 @@ struct RISCVCPU { > bool ext_s; > bool ext_u; > bool ext_h; > + bool ext_j; > bool ext_v; > bool ext_counters; > bool ext_ifencei; > -- > 2.20.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6339e84819..d152842e37 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -72,6 +72,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -285,6 +286,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_counters; bool ext_ifencei;