diff mbox series

[05/15] hw/riscv: sifive_gpio: Clean up the codes

Message ID 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com
State New
Headers show
Series hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support | expand

Commit Message

Bin Meng June 8, 2020, 2:17 p.m. UTC 
From: Bin Meng <bin.meng@windriver.com>

Do various minor clean-ups to the exisiting codes for:

- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/sifive_gpio.c         | 13 +++++--------
 include/hw/riscv/sifive_gpio.h |  7 ++++---
 2 files changed, 9 insertions(+), 11 deletions(-)

Comments

Alistair Francis June 15, 2020, 4:13 p.m. UTC | #1 
On Mon, Jun 8, 2020 at 7:22 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Do various minor clean-ups to the exisiting codes for:
>
> - coding convention conformance
> - remove unnecessary blank lines
> - spell SiFive correctly
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/sifive_gpio.c         | 13 +++++--------
>  include/hw/riscv/sifive_gpio.h |  7 ++++---
>  2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index 5c7c596..c9cffa2 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -1,5 +1,5 @@
>  /*
> - * sifive System-on-Chip general purpose input/output register definition
> + * SiFive System-on-Chip general purpose input/output register definition
>   *
>   * Copyright 2019 AdaCore
>   *
> @@ -20,7 +20,6 @@
>
>  static void update_output_irq(SIFIVEGPIOState *s)
>  {
> -
>      uint32_t pending;
>      uint32_t pin;
>
> @@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
>  }
>
>  static void sifive_gpio_write(void *opaque, hwaddr offset,
> -                       uint64_t value, unsigned int size)
> +                              uint64_t value, unsigned int size)
>  {
>      SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
>
> @@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
>      s->out_xor = 0;
>      s->in = 0;
>      s->in_mask = 0;
> -
>  }
>
>  static const VMStateDescription vmstate_sifive_gpio = {
> @@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
>          VMSTATE_UINT32(iof_en,    SIFIVEGPIOState),
>          VMSTATE_UINT32(iof_sel,   SIFIVEGPIOState),
>          VMSTATE_UINT32(out_xor,   SIFIVEGPIOState),
> -        VMSTATE_UINT32(in, SIFIVEGPIOState),
> -        VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
> +        VMSTATE_UINT32(in,        SIFIVEGPIOState),
> +        VMSTATE_UINT32(in_mask,   SIFIVEGPIOState),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> @@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
>              TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
>      sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>
> -
>      for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
>          sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
>      }
> @@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data)
>
>      dc->vmsd = &vmstate_sifive_gpio;
>      dc->reset = sifive_gpio_reset;
> -    dc->desc = "sifive GPIO";
> +    dc->desc = "SiFive GPIO";
>  }
>
>  static const TypeInfo sifive_gpio_info = {
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
> index fce03d6..ad915b2 100644
> --- a/include/hw/riscv/sifive_gpio.h
> +++ b/include/hw/riscv/sifive_gpio.h
> @@ -1,5 +1,5 @@
>  /*
> - * sifive System-on-Chip general purpose input/output register definition
> + * SiFive System-on-Chip general purpose input/output register definition
>   *
>   * Copyright 2019 AdaCore
>   *
> @@ -10,10 +10,12 @@
>   * This code is licensed under the GPL version 2 or later.  See
>   * the COPYING file in the top-level directory.
>   */
> +
>  #ifndef SIFIVE_GPIO_H
>  #define SIFIVE_GPIO_H
>
>  #include "hw/sysbus.h"
> +
>  #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
>  #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
>
> @@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
>      uint32_t out_xor;
>      uint32_t in;
>      uint32_t in_mask;
> -
>  } SIFIVEGPIOState;
>
> -#endif
> +#endif /* SIFIVE_GPIO_H */
> --
> 2.7.4
>
>
diff mbox series

Patch

diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 5c7c596..c9cffa2 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -1,5 +1,5 @@ 
 /*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
  *
  * Copyright 2019 AdaCore
  *
@@ -20,7 +20,6 @@ 
 
 static void update_output_irq(SIFIVEGPIOState *s)
 {
-
     uint32_t pending;
     uint32_t pin;
 
@@ -186,7 +185,7 @@  static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
 }
 
 static void sifive_gpio_write(void *opaque, hwaddr offset,
-                       uint64_t value, unsigned int size)
+                              uint64_t value, unsigned int size)
 {
     SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
 
@@ -318,7 +317,6 @@  static void sifive_gpio_reset(DeviceState *dev)
     s->out_xor = 0;
     s->in = 0;
     s->in_mask = 0;
-
 }
 
 static const VMStateDescription vmstate_sifive_gpio = {
@@ -342,8 +340,8 @@  static const VMStateDescription vmstate_sifive_gpio = {
         VMSTATE_UINT32(iof_en,    SIFIVEGPIOState),
         VMSTATE_UINT32(iof_sel,   SIFIVEGPIOState),
         VMSTATE_UINT32(out_xor,   SIFIVEGPIOState),
-        VMSTATE_UINT32(in, SIFIVEGPIOState),
-        VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
+        VMSTATE_UINT32(in,        SIFIVEGPIOState),
+        VMSTATE_UINT32(in_mask,   SIFIVEGPIOState),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -356,7 +354,6 @@  static void sifive_gpio_init(Object *obj)
             TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 
-
     for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
         sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
     }
@@ -371,7 +368,7 @@  static void sifive_gpio_class_init(ObjectClass *klass, void *data)
 
     dc->vmsd = &vmstate_sifive_gpio;
     dc->reset = sifive_gpio_reset;
-    dc->desc = "sifive GPIO";
+    dc->desc = "SiFive GPIO";
 }
 
 static const TypeInfo sifive_gpio_info = {
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index fce03d6..ad915b2 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -1,5 +1,5 @@ 
 /*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
  *
  * Copyright 2019 AdaCore
  *
@@ -10,10 +10,12 @@ 
  * This code is licensed under the GPL version 2 or later.  See
  * the COPYING file in the top-level directory.
  */
+
 #ifndef SIFIVE_GPIO_H
 #define SIFIVE_GPIO_H
 
 #include "hw/sysbus.h"
+
 #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
 #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
 
@@ -66,7 +68,6 @@  typedef struct SIFIVEGPIOState {
     uint32_t out_xor;
     uint32_t in;
     uint32_t in_mask;
-
 } SIFIVEGPIOState;
 
-#endif
+#endif /* SIFIVE_GPIO_H */